NDLI: An efficient surface potential solution algorithm for compact MOSFET models

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2015 IEEE International Electron Devices Meeting (IEDM)

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IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.

IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004.

IEEE International Electron Devices Meeting 2004 - IEDM Technical Digest - Title

Welcome from the General Chair

The beginnings of the IEDM

Award presentations

IEDM Executive Committee

Session quick index

Table of contents

Plenary session

IEDM - a view as a participant and a customer

Future semiconductor manufacturing: challenges and opportunities

Emerging technologies on silicon

Displays, sensors and MEMS - MEMS technologies and applications [breaker page]

High-speed MEMS-based gas chromatography

A reliable and compact polymer-based package for capacitive RF-MEMS switches

Fully integrated CMOS and high voltage compatible RF MEMS technology

Post-fabrication laser trimming of micromechanical filters

A trench-sidewall single-wafer-MEMS technology and its typical application in high-performance accelerometers

An electrothermally-actuated, dual-mode micromirror for large bi-directional scanning

Novel ferroelectrics-based micro-acoustic devices and their ultrasonic applications

Session 3 - Integrated Circuits and Manufacturing DRAM

Highly scalable sub-50nm vertical double gate trench DRAM cell

Enhanced data retention of damascene-finFET DRAM with local channel implantation and <100> fin surface orientation engineering

Lattice strain design in W/WN/poly-Si gate DRAM for improving data retention time

A mechanically enhanced storage node for virtually unlimited height (MESH) capacitor aiming at sub 70nm DRAMs

A highly manufacturable deep trench based DRAM cell layout with a planar array device in a 70nm technology

Session 4 - Process Technology Fully-Silicided (FUSI) Gates

Advanced gate stacks with fully silicided (FUSI) gates and high-/spl kappa/ dielectrics: enhanced performance at reduced gate leakage

Partial silicides technology for tunable work function electrodes on high-k gate dielectrics - Fermi level pinning controlled PtSi/sub x/ for HfO/sub x/ (N) pMOSFET

Work function tuning through dopant scanning and related effects in Ni fully silicided gate for sub-45nm nodes CMOS

Dual workfunction Ni-Silicide/HfSiON gate stacks by phase-controlled full-silicidation (PC-FUSI) technique for 45nm-node LSTP and LOP devices

Proposal of new HfSiON CMOS fabrication process (HAMDAMA) for low standby power device

Diffusion-less junctions and super halo profiles for PMOS transistors formed by SPER and FUSI gate in 45 nm physical gate length devices

Session 5 - CIVIOS and Interconnect Reliability - NBTI Effect in Conventional and High-K Dielectrics

Mechanism of negative bias temperature instability in CMOS devices: degradation, recovery and impact of nitrogen

On-the-fly characterization of NBTI in ultra-thin gate oxide PMOSFET's

A geometrical unification of the theories of NBTI and HCI time-exponents and its implications for ultra-scaled planar and surround-gate MOSFETs

Influence of nitrogen in ultra-thin SiON on negative bias temperature instability under AC stress

Negative bias temperature instabilities in HfSiON/TaN-based pMOSFETs

HCI and BTI characteristics of ALD HfSiO(N) gate dielectrics as the compositions and the post treatment conditions

Physical model of BTI, TDDB and SILC in HfO/sub 2/-based high-k gate dielectrics

Session 6 - Modeling and Simulation Transport in Nanoscale Silicon-Based FETs - I

Simulation study of Ge n-channel 7.5 nm DGFETs of arbitrary crystallographic alignment

Bandstructure effects in ballistic nanoscale MOSFETs

Relevance of remote scattering in gate to channel mobility of thin-oxide CMOS devices

Quantum mechanical calculation of hole mobility in silicon inversion layers under arbitrary stress

Impact of surface roughness on silicon and germanium ultra-thin-body MOSFETs

Session 7 - CMOS Devices - Strained Silicon I

Selectively formed high mobility strained Ge PMOSFETs for high performance CMOS

Low power device technology with SiGe channel, HfSiON, and poly-Si gate

Performance comparison and channel length scaling of strained Si FETs on SiGe-on-insulator (SGOI)

Impact of parasitic resistance and silicon layer thickness scaling for strained-silicon MOSFETs on relaxed Si/sub 1-x/Ge/sub x/ virtual substrate

High electron and hole mobility enhancements in thin-body strained Si/strained SiGe/strained Si heterostructures on insulator

Performance enhancement of partially- and fully-depleted strained-SOI MOSFETs and characterization of strained-Si device parameters

3D GOI CMOSFETs with novel IrO/sub 2/(Hf) dual gates and high-k dielectric on 1P6M-0.18 /spl mu/m-CMOS

Session 8 - Solid State Devices - Room Temperature Single Electronics and Tunneling Devices

Room-temperature demonstration of integrated silicon single-electron transistor circuits for current switching and analog pattern matching

2004Transistor in a test tube - harnessing molecular biology to the self-assembly of molecular scale electronics

The tunneling field effect transistor (TFET) as an add-on for ultra-low-voltage analog and digital processes

Room-temperature single-electron transfer and detection with silicon nanodevices

80nm self-aligned complementary I-MOS using double sidewall spacer and elevated drain structure and its applicability to amplifiers with high linearity

Session 9 - CMOS Devices - Strained Silicon - II

Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs

A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films

Mobility improvement for 45nm node by combination of optimized stress and channel orientation design

Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs

In-plane mobility anisotropy and universality under uni-axial strains in nand p-MOS inversion layers on (100), [110], and (111) Si

Experimental study of biaxial and uniaxial strain effects on carrier mobility in bulk and ultrathin-body SOI MOSFETs

Package-strain-enhanced device and circuit performance

Session 10 - Solid State Devices - SiGe HBTs

Integration of high-performance SiGe:C HBTs with thin-film SOI CMOS

Metal emitter SiGe:C HBTs

SiGe HBT technology with f/sub max//f/sub T/=350/300 GHz and gate delay below 3.3 ps

A low-parasitic collector construction for high-speed SiGe:C HBTs

3.3 ps SiGe bipolar technology

Session 11- Integrated Circuits and Manufacturing - SRAM and SOI-Based Memories

Aggressively scaled (0.143 /spl mu/m/sup 2/) 6T-SRAM cell for the 32 nm node and beyond

Highly area efficient and cost effective double stacked S/sup 3/ (stacked single-crystal Si) peripheral CMOS SSTFT and SRAM cell technology for 512M bit density SRAM

A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography

Fully planar 0.562/spl mu/m/sup 2/ T-RAM cell in a 130nm SOI CMOS logic technology for high-density high-performance SRAMs

A capacitor-less DRAM cell on 75nm gate length, 16nm thin fully depleted SOI device for high density embedded memories

Fully-depleted FBC (floating body cell) with enlarged signal window and excellent logic process compatibility

Session 12 - Process Technology - Metal Gate Engineering and Integration

Challenges for the integration of metal gate electrodes

Poly-gate replacement through contact hole (PRETCH): a new method for high-k/metal gate and multi-oxide implementation on chip

Evaluation of Fermi level pinning in low, midgap and high workfunction metal gate electrodes on ALD and MOCVD HfO/sub 2/ under high temperature exposure

Substituted aluminum metal gate on high-k dielectric for low work-function and Fermi-level pinning free

A novel methodology on tuning work function of metal gate using stacking bi-metal layers

Germanium p- & n-MOSFETs fabricated with novel surface passivation (plasma-PH/sub 3/ and thin AlN) and TaN/HfO/sub 2/ gate stack

Session 13 - Process Technology - Advanced Interconnect Technologies

Challenges in Cu/low-k integration

Demonstration of an extendable and industrial 300mm BEOL integration for the 65-nm technology node

Successful dual damascene integration of extreme low k materials (k < 2.0) using a novel gap fill based integration scheme

Integration of ALD TaN barriers in porous low-k interconnect for the 45 nm node and beyond; solution to relax electron scattering effect

Challenge of low-k materials for 130, 90, 65 nm node interconnect technology and beyond

A novel solution for porous low-k dual damascene post etch stripping/clean with supercritical CO/sub 2/ technology for 65nm and beyond applications

Direct plating of Cu on ALD TaN for 45nm node Cu BEOL metallization

Session 14 - Quantum Electronics and Compound Semiconductors - The New Spectrum of Optoelectronic Devices

{113} defect-engineered silicon light-emitting diodes

255 nm interconnected micro-pixel deep ultraviolet light emitting diodes

High-responsivity, high-speed, and high-saturation-power performances of evanescently coupled photodiodes with partially p-doped photo-absorption layer

Novel infrared phototransistors for atmospheric CO/sub 2/ profiling at 2 /spl mu/m wavelength

Photonic crystals: fundamentals and applications

Session 15 - Displays, Sensors and MEMS - Organic TFT's and Devices on Flexible Substrates

A large-area, flexible, and lightweight sheet image scanner integrated with organic field-effect transistors and organic photodiodes

Low-voltage flexible organic circuits with molecular gate dielectrics

TES anthradithiophene solution-processed OTFTs with 1 cm/sup 2//V-s mobility

An organic semiconductor based process for photodetecting applications

Process control of threshold voltage in organic FETs

OLED pixel array on a dome

Session 16 - Modeling and Simulation - Reliability

Inversion mobility and gate leakage in high-k/metal gate MOSFETs

Analysis on data retention time of nano-scale DRAM and its prediction by probing the tail cell leakage current

Modeling of retention time distribution of DRAM cell using a Monte-Carlo method

A comprehensive trapped charge profiling technique for SONOS flash EEPROMs

Experimental extraction of the electron impact-ionization coefficient at large operating temperatures

Electro-thermal comparison and performance optimization of thin-body SOI and GOI MOSFETs

Power optimization of future transistors and a resulting global comparison standard

Session 17 - CMOS Devices - Aggressively Scaled Planar MOSFETs

Circuit techniques for subthreshold leakage avoidance, control and tolerance

A conventional 45nm CMOS node low-cost platform for general purpose and low power applications

Transport properties of sub-10-nm planar-bulk-CMOS devices

Direct evaluation of gate line edge roughness impact on extension profiles in sub-50nm N-MOSFETs

Double SiGe:C diffusion barrier channel 40nm CMOS with improved short-channel performances

Record RF performance of standard 90 nm CMOS technology

Session 18 - Solid State Devices - Power, RF, and Passives Technology

High-voltage extension(V/sub BR/ /spl ges/ 800 V) for smart-power SOI-technologies

High voltage devices - a milestone concept in power ICs

RF power potential of 90 nm CMOS: device options, performance, and reliability

Lateral IMPATT diodes in standard CMOS technology

New low-cost thermally stable process to reduce silicon substrate: a way to extreme frequencies for high volume Si technologies

Novel differential inductor design for high self-resonance frequency

Session 19 - CMOS and Interconnect Reliability - Process Induced and Electrical Degradation in Flash Memories and CMOS Circuits

Ionizing radiation effects on MOSFET thin and ultra-thin gate oxides

Low leakage reliability characterization methodology for advanced CMOS with gate oxide in the 1nm range

Implant damage and gate-oxide-edge effects on product reliability

Charge trapping effects in HfSiON dielectrics on the ring oscillator circuit and the single stage inverter operation

What we have learned on flash memory reliability in the last ten years

High energy oxide traps and anomalous soft-programming in flash memories

Session 20 - Process Technology High-k I: Hafnium-Silicate Dielectrics

Careful examination on the asymmetric Vfb shift problem for poly-Si/HfSiON gate stack and its solution by the Hf concentration control in the dielectric near the poly-Si interface with small EOT expense

The effects of TaN thickness and strained substrate on the performance and PBTI characteristics of poly-Si/TaN/HfSiON MOSFETs

Impact of Hf concentration on performance and reliability for HfSiON-CMOSFET

Characteristics of ALD HfSiO/sub x/ using new Si precursors for gate dielectric applications

Implementation of HfSiON gate dielectric for sub-60nm DRAM dual gate oxide with recess channel array transistor (RCAT) and tungsten gate

Session 21 - Emerging Technologies Nano-Computing Devices

Nanowires: building blocks for the assembly of integrated nanosystems

Carbon nanotube electronics and optoelectronics

Self-assembled monolayer molecular devices

Electron spin qubits in quantum dots

Spintronics: semiconductors, molecules and quantum information

Mechanical compution, redux? [Nanoelectromechanical systems]

Session 22 - Ouantum Electronics and Compound Semiconductors - Superscaled, Ultrafast HBTs

Polymer based technologies for microwave and millimeterwave applications

0.25 /spl mu/m emitter InP SHBTs with f/sub T/ = 550 GHz and BV/sub CEO/ > 2V

First demonstration of sub-0.25/spl mu/m-width emitter InP-DHBTs with > 400 GHz f/sub t/ and > 400 GHz f/sub max/

Ultra high-speed 0.25-/spl mu/m emitter InP-InGaAs SHBTs with f/sub max/ of 687 GHz

Flip-chip mounted 26 V GaInP/GaAs power HBTs

Session 23 - Integrated Circuits and Manufacturing - Non-Volatile Memory Technology; MRAM, RRAM AND FERAM

Status and outlook of emerging nonvolatile memory technologies

Design and process integration for high-density, high-speed, and low-power 6F/sup 2/ cross point MRAM cell

High density and low power design of MRAM

A 0.13/spl mu/m MRAM with 0.26/spl times/0.44/spl mu/m/sup 2/ MTJ optimized on universal MR-RA relation for 1.2V high-speed operation beyond 143MHz

Improvement of robustness against write disturbance by novel cell design for high density MRAM

Highly scalable nonvolatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses

Fully logic compatible (1.6V Vcc, 2 additional FRAM masks) highly reliable sub 10F2 embedded FRAM with advanced direct via technology and robust 100 nm thick MOCVD PZT technology

Session 24 - Modeling and Simulation - Transport in Nanoscale Silicon-Based FETs-II

Scaling study of Si and strained Si n-MOSFETs with different high-k gate stacks

Exploring the limit of strain-induced performance gain in p- and n-SSDOI-MOSFETs

A Monte-Carlo study of the role of scattering in deca-nanometer MOSFETs

Enhanced ballisticity in nano-MOSFETs along the ITRS roadmap: a Monte Carlo study

Pragmatic design of nanoscale multi-gate CMOS

3D quantum modeling and simulation of multiple-gate nanowire MOSFETs

What will end CMOS scaling - money or physics? [Panel Discussion Topics]

Nanoelectronics - now or never? [Panel Discussion Topics]

Session 27 - CMOS Devices - Novel SOI and Multi-Channel MOSFETs

Sub 30 nm multi-bridge-channel MOSFET (MBCFET) with metal gate electrode for ultra high performance application

Silicon on thin BOX: a new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control

SON (silicon-on-nothing) technological CMOS platform: highly performant devices and SRAM cells

A novel multi-channel field effect transistor (McFET) on bulk Si for high performance sub-80nm application

Molybdenum gate HfO/sub 2/ CMOS FinFET technology

Large scale integration and reliability consideration of triple gate transistors

Session 28 - Integrated Circuits and Manufacturing - Advanced Logic and Platform Technologies

SoC integration in deep submicron CMOS

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell

High performance and low power transistors integrated in 65nm bulk CMOS technology

A 65 nm CMOS technology for mobile and digital signal processing applications

A novel low cost 65nm CMOS process architecture with self aligned isolation and W cladded source/drain

Customer oriented technologies for innovative leading edge foundry manufacturing

On-chip transmission line for long global interconnects

Session 29 - Solid State Devices - Next Generation Devices

Carbon nanotubes for interconnect applications

Novel carbon nanotube FET design with tunable polarity

High frequency S parameters characterization of back-gate carbon nanotube field-effect transistors

Self-aligned carbon nanotube transistors with novel chemical doping

Performance comparison between carbon nanotube and copper interconnects for GSI

Performance analysis and design optimization of near ballistic carbon nanotube field-effect transistors

Modulation of drain current by redox-active molecules incorporated in Si MOSFETs

Session 30 - CMOS and Interconnect Reliability - Gate Dielectric Reliability - Breakdown, and Device Degradation Mechanism

Implications of progressive wear-out for lifetime extrapolation of ultra-thin (EOT /spl sim/ 1 nm) SiON films

New insight into gate dielectric breakdown induced MOSFET degradation by novel percolation path resistance measurements

Model for dielectric breakdown mechanism of HfAlO/sub x//SiO/sub 2/ stacked gate dielectrics dominated by the generated subordinate carrier injection

A comprehensive model for breakdown mechanism in HfO/sub 2/ high-k gate stacks

Charge trapping in aggressively scaled metal gate/high-k stacks

Negative U traps in HfO/sub 2/ gate dielectrics and frequency dependence of dynamic BTI in MOSFETs

Characterization and modeling of hysteresis phenomena in high K dielectrics

Session 31- Modeling and Simulation - Compact Modeling

A new cell-based performance metric for novel CMOS device architectures

Predictive compact modeling of NQS effects and thermal noise in 90nm mixed-signal/RF CMOS technology

Capacitance modeling of laterally non-uniform MOS devices

An efficient surface potential solution algorithm for compact MOSFET models

Modeling of RTS noise in MOSFETs under steady-state and large-signal excitation

A compact QM-based mobility model for nanoscale ultra-thin-body CMOS devices

Session 32 - Displays, Sensors and MEMS - Thin Film Transistors

A novel transparent air-stable printable n-type semiconductor technology using ZnO nanoparticles

Single-grain TFTs on location-controlled crystal grains formed by excimer laser crystallization of Si thin films

High performance and high reliability polysilicon thin-film transistors with multiple nano-wire channels

A novel methodology for extracting effective density-of-states in poly-Si thin-film transistors

Analytical photo leak current model of low-temperature CW laser lateral crystallization (CLC) poly-Si TFTs

Impact of transistor-to-grain size statistics on large-grain polysilicon TFT characteristics

Session 33 - Quantum Electronics and Compound Semiconductors - GaN-based Power Devices

Recent advances in III-V nitride electronic devices

A 100-W high-gain AlGaN/GaN HEMT power amplifier on a conductive n-SiC substrate for wireless base station applications

350V/150A AlGaN/GaN power HFET on silicon substrate with source-via grounding (SVG) structure

GaN double heterojunction field effect transistor for microwave and millimeterwave power applications

Al/sub 0.3/Ga/sub 0.7/N/Al/sub 0.05/Ga/sub 0.95/N/GaN composite-channel HEMTs with enhanced linearity

Edge trapping mechanism of current collapse in III-N FETs

Session 34 - Process Technology - High-k II: Interfaces and Materials Properties

Improved short channel device characteristics with stress relieved pre-oxide (SRPO) and a novel tantalum carbon alloy metal gate/HfO/sub 2/ stack

Interface engineering for enhanced electron mobilities in W/HfO/sub 2/ gate stacks

Impact of oxygen vacancies on high-/spl kappa/ gate stack engineering

Depletion-free poly-Si gate high-k CMOSFETs

Improved electrical and material characteristics of hafnium titanate multi-metal oxide n-MOSFETs with ultra-thin EOT (/spl sim/8 /spl Aring/) gate dielectric application

A robust alternative for the DRAM capacitor of 50 nm generation

Session 35 - CMOS Devices Advanced - Gate-Stack Devices

Gate stack optimization for 65 nm CMOS low power and high performance platform

45 nm nMOSFET with metal gate on thin SiON driving 1150 /spl mu/A//spl mu/m and off-state of 10nA//spl mu/m

Work function engineering by FUSI and its impact on the performance and reliability of oxynitride and Hf-silicate based MOSFETs

Intrinsic characteristics of high-k devices and implications of fast transient charging effects (FTCE)

Ultra-fast measurements of the inversion charge in MOSFETs and impact on measured mobility in high-k MOSFETs

Experimental determination of mobility scattering mechanisms in Si/HfO/sub 2//TiN and SiGe:C/HfO/sub 2//TiN surface channel n- and p-MOSFETs

Session 36 - Integrated Circuits and Manufacturing - Floating-Gate and Discrete Trap Non-Volatile Memory

8 Gb MLC (multi-level cell) NAND flash memory using 63 nm process technology

Impact of few electron phenomena on floating-gate memory reliability

A novel 2-bit/cell nitride storage flash memory with greater than 1M P/E-cycle endurance

Impact of SiON on embedded nonvolatile MNOS memory

High-k HfAlO charge trapping layer in SONOS-type nonvolatile memory device for high speed operation

Damascene gate FinFET SONOS memory implemented on bulk silicon wafer

Impact of stoichiometry control in double junction memory on future scaling

Session 37 - Solid State Devices Emerging Memories

Spintronic materials and devices: past, present and future!

Highly manufacturable high density phase change memory of 64Mb and beyond

Electrothermal and phase-change dynamics in chalcogenide-based memories

Long-retention ferroelectric-gate FET with a (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ buffer-insulating layer for 1T FeRAM

Scalability study on a capacitorless 1T-DRAM: from single-gate PD-SOI to double-gate FinDRAM

A new vertically stacked poly-Si MOSFET for 533 MHz high speed 64Mbit SRAM

Integration of manufacturable 65nm-node HfSiON transistors optimized with low-thermal-budget CMOS process

SESSION 38: CMOS and interconnect reliability ESD, soft errors and backend reliability issues for nanoscale CMOS technologies

ESD and latch-up reliability for nanometer CMOS technologies

Transient-induced latchup in CMOS technology: physical mechanism and device simulation

Comprehensive study of soft errors in advanced CMOS circuits with 90/130 nm technology

Investigation of soft error rate including multi-bit upsets in advanced SRAM using neutron irradiation test and 3D mixed-mode device simulation

Enhanced dielectric-constant reliability of low-k porous organosilicate glass (k = 2.3) for 45-nm-generation Cu interconnects

Thermally robust Cu interconnects with Cu-Ag alloy for sub 45nm node

Effect of mechanical strength and residual stress of dielectric capping layer on electromigration performance in Cu/low-k interconnects

Modeling and simulation process modeling [Session 39]

Front end stress modeling for advanced logic technologies

On the modeling of transient diffusion and activation of boron during post-implantation annealing

Electrical deactivation and diffusion of boron in preamorphized ultrashallow junctions: interstitial transport and F co-implant control

Simulation of high-temperature millisecond annealing-based on atomistic modeling of boron diffusion/activation in silicon

Transient behavior of phosphorus dose loss and modeling of dopant segregation at the Si/SiO/sub 2/ interface

Experimental and simulation study of boron segregation and diffusion during gate oxidation and spike annealing

Detectors, sensors and displays image sensors and bio sensors

Device technologies for high quality and smaller pixel in CCD and CMOS image sensors

Dark current reduction in very-large area CCD imagers for professional DSC applications

Crosstalk improvement technology applicable to 0.14/spl mu/m CMOS image sensor

MOSFETs and high-speed photodetectors on Ge-on-insulator substrates fabricated using rapid melt growth

A highly manufacturable nano-metallic particle based DNA micro-array

Label-free detection of DNA hybridization with Au/SiO/sub 2//Si diodes and poly-Si TFTs

Three-dimensional multichannel Si microprobe electrode array chip for analysis of the nervous system

Quantum electronics and compound semiconductors HEMTs: physics and now technologies

Thermal, electrical and environmental reliability of InP HEMTs and GaAs PHEMTs

100nm InAlAs/InGaAs double-gate HEMT using transferred substrate

Suppression of kink phenomenon in ultra-high-speed strained InAs- inserted E-mode HEMTs with a new 0.1 /spl mu/m Y-shaped Pt-buried gate and their impacts on device performance

Growth and characterization of AlGaN/AlN/GaN HEMTs on 100-mm-diameter epitaxial AlN/sapphire templates

Polarization engineering of InAlN/GaN HFET and the effect on DC and RF performance

Universal signature of ballistic transport in nanoscale field effect transistors

Process technology - advances in source drain engineering [Session 42]

Front-end-of-line (FEOL) optimization for high-performance, high-reliable strained-Si MOSFETs; from virtual substrate to gate oxidation

Highly controllable cyclic selective epitaxial growth (CySEG) for 65nm CMOS technology and beyond

A systematic study of trade-offs in engineering a locally strained pMOSFET

Drastic suppression of thermally induced leakage of NiSi silicided shallow junctions by pre-SALICIDE fluorine implantation

A highly manufacturable low-k ALD-SiBN process for 60nm NAND flash devices and beyond

Late news! International Electron Devices Meeting 2004 - IEDM Technical Digest

Enhanced performance in 50 nm N-MOSFETs with silicon-carbon source/drain regions

A high-performance all-inkjetted organic transistor technology

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

High-gain microwave GaN HEMTs with source-terminated field-plates

High performance multi-bit nonvolatile HfO/sub 2/ nanocrystal memory using spinodal phase separation of hafnium silicate

20 nm tri-gate SONOS memory cells with multi-level operation

IEEE IEDM [Back Cover]

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