NDLI: Issues in modeling small devices

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International Electron Devices Meeting 1999. Technical Digest [Front Matter and Table of Contents]

Consumer electronics as silicon engine

SoC solutions and technologies for digital hypermedia platform

Sorting of biontolecules via microdevices

A novel trench DRAM cell with a vertical access transistor and buried strap (VERI BEST) for 4 Gb/16 Gb

A novel cell-STP (storage node through plate node) cell-technology for multigigabit-scale DRAM and logic-embedded DRAM generations

Extending trench DRAM technology to 0.15 /spl mu/m groundrule and beyond

Impact of the two traps related leakage mechanism on the tail distribution of DRAM retention characteristics

An embedded 0.405 /spl mu/m/sup 2/ stacked DRAM technology integrated with high-performance 0.2 /spl mu/m CMOS logic and 6-level metalization

A high-performance 0.18-/spl mu/m merged DRAM/Logic technology featuring 0.45-/spl mu/m/sup 2/ stacked capacitor cell

Thermally robust dual-gate CMOS integration technologies for high-performance DRAM-embedded ASICs

The ballistic nano-transistor

A new SOI MOSFET structure with junction type body contact

A novel sidewall strained-Si channel nMOSFET

Sub 50-nm FinFET: PMOS

Super self-aligned double-gate (SSDG) MOSFETs utilizing oxidation rate difference and selective epitaxy

The Vertical Replacement-Gate (VRG) MOSFET: a 50-nm vertical MOSFET with lithography-independent gate length

Device reliability in analog CMOS applications

Mechanism for hot-carrier-induced interface trap generation in MOS transistors

Channel hot-electron and hot-hole improvement in Al and Cu multilevel metal CMOS using deuterated anneals and passivating films

Improved charge-pumping method for lateral profiling of interface traps and oxide charge in MOSFET devices

Plasma process-induced damage in SOI devices

Investigation of plasma-induced charging damage for nMOSFETs with conventional or damascene Al interconnects

Technology for active matrix light emitting polymer displays

High-mobility, low voltage organic thin film transistors

Novel fabrication methods and characteristics of organic complementary circuits

High temperature polycrystalline silicon thin film transistor on steel substrates

Optical devices fabricated from porous thin films embedded with liquid crystals

Two-dimensional nozzle arrangement in a monolithic inkjet printhead for high-resolution and high-speed printing

Ultrathin hafnium oxide with low leakage and excellent reliability for alternative gate dielectric application

High quality ultra-thin (1.5 nm) TiO/sub 2/-Si/sub 3/N/sub 4/ gate dielectric for deep sub-micron CMOS technology

High quality Ta/sub 2/O/sub 5/ gate dielectrics with T/sub ox.eq/<10 /spl Aring/

MOSCAP and MOSFET characteristics using ZrO/sub 2/ gate dielectric deposited directly on Si

Zirconium oxide based gate dielectrics with equivalent oxide thickness of less than 1.0 nm and performance of submicron MOSFET using a nitride gate replacement process

Accurate thermal noise model for deep-submicron CMOS

Fluctuations of the low frequency noise of MOS transistors and their modeling in analog and RF-circuits

A large signal non-quasi-static MOS model for RF circuit simulation

A comprehensive MOSFET mismatch model

Modeling of pocket implanted MOSFETs for anomalous analog behavior

Self-heating characterization for SOI MOSFET based on AC output conductance

A Spice-compatible flash EEPROM model feasible for transient and program/erase cycling endurance simulation

Current and future development of high power MOS devices

High voltage NPN-bipolar transistor using P/sup +/-buried layer in BiCMOS process

Snapback and safe operating area of LDMOS transistors

20 V and 8 V lateral trench gate power MOSFETs with record-low on-resistance

RF LDMOS with extreme low parasitic feedback capacitance and high hot-carrier immunity

High performance scaled down Si LDMOSFET with thin gate bird's beak technology for RF power amplifiers

High temperature (450/spl deg/C) reliable NMISFET's on p-type 6H-SiC

Magnetoelectronic devices

Design and demonstration of new operation mode multi-emitter resonant tunneling hot electron transistors for one-transistor-SRAM-cell and peripheral logic circuitry

Resonant Fowler-Nordheim tunneling through layered tunnel barriers and its possible applications

Prospects for molecular-scale devices

Molecular-scale rectifying diodes based on Y-junction carbon nanotubes

Memory operation of AlGaAs/GaAs heterostructure FETs with InAs quantum dots in an AlGaAs barrier layer

MOSFETs with 9 to 13 A thick gate oxides

Integration of ultrathin (1.6/spl sim/2.0 nm) RPECVD oxynitride gate dielectrics into dual poly-Si gate submicron CMOSFETs

Low-temperature growth of high-integrity silicon oxide films by oxygen radical generated in high-density krypton plasma

A novel W/TiNx metal gate CMOS technology using nitrogen-concentration-controlled TiNx film

Reduction of threshold voltage deviation in Damascene metal gate MOSFETs

Cu/poly-Si damascene gate structured MOSFET with Ta and TaN stacked barrier

A high density high performance 180 nm generation Etox/sup TM/ flash memory technology

A novel gate-offset NAND cell (GOC-NAND) technology suitable for high-density and low-voltage-operation flash memories

The scaling properties of CHISEL and CHE injection efficiency in MOSFETs and flash memory cells

Highly manufacturable 1T1C 4 Mb FRAM with novel sensing scheme

A novel thyristor-based SRAM cell (T-RAM) for high-speed, low-voltage, giga-scale memories

Surface free technology by laser annealing (SUFTLA)

Single grain thin-film-transistor (TFT) with SOI CMOS performance formed by metal-induced-lateral-crystallization

Reproducible high field effect mobility polysilicon thin film transistors involving pulsed Nd:YVO/sub 4/ laser crystallization

Limit of the mobility enhancement of the excimer-laser-crystallized low-temperature poly-Si TFTs

Effects of plasma treatments, substrate types, and crystallization methods on performance and reliability of low temperature polysilicon TFTs

Hydrogenated amorphous-silicon thin-film transistor structure with buried field plate

Soft error considerations for deep-submicron CMOS circuit applications

The metal gate MOS reliability with improved sputtering process for gate electrode

Role of base layer in CVD Si/sub 3/N/sub 4/ stack gate dielectrics on the process controllability and reliability in direct tunneling regime

Analysis of high voltage TDDB measurements on Ta/sub 2/O/sub 5//SiO/sub 2/ stack

Fundamental diffusion issues for deep-submicron device processing

Dopant redistribution in SOI during RTA: a study on doping in scaled-down Si layers

Anomalous diffusion of dopant in Si substrate during oxynitride process

Dopant diffusion in C-doped Si and SiGe: physical model and experimental verification

Two-dimensional dopant characterization using SIMS, SCS and TSUPREM4

Predictive BSIM3v3 modeling for the 0.15-0.18 /spl mu/m CMOS technology node: a process DOE based approach

Determination of stress in shallow trench isolation for deep submicron MOS devices by UV Raman spectroscopy

Single electron and few electron memory cells

Si complementary single-electron inverter

A directional current switch using silicon single electron transistors controlled by charge injection into silicon nano-crystal floating dots

Write, erase and storage times in nanocrystal memories and the role of interface states

Threshold voltage increase by quantum mechanical narrow channel effect in ultra-narrow MOSFETs

Coulomb oscillations in 100 nm and 50 nm CMOS devices

Wide bandgap semiconductor microwave technologies: from promise to practice

200 W GaAs-based MODFET power amplifier for W-CDMA base stations

Microwave performance of AlGaN/GaN high electron mobility transistors on Si(111) substrates

Recessed gate AlGaN/GaN MODFET on sapphire grown by MOCVD

A low-distortion and high-efficiency E-mode GaAs power FET based on a new method to improve device linearity focused on g/sub m/ value

A 25 GHz InGaAs/InAlAs-InP HBT power MMIC with 48% power added efficiency

100 nm gate length high performance/low power CMOS transistor structure

A 1.2V, sub-0.09 /spl mu/m gate length CMOS technology

Device issues in the integration of analog/RF functions in deep submicron digital CMOS

High performance transistors with state-of-the-art CMOS technologies

Sub-60 nm physical gate length SOI CMOS

Gate oxides in 50 nm devices: thickness uniformity improves projected reliability

Nonlinear characteristics of Weibull breakdown distributions and its impact on reliability projection for ultra-thin oxides

A consistent model for time dependent dielectric breakdown in ultrathin silicon dioxides

Explanation of soft and hard breakdown and its consequences for area scaling

Analysis of tunneling currents and reliability of NMOSFETs with sub-2 nm gate oxides

Minority carrier tunneling and stress-induced leakage current for p/sup +/ gate MOS capacitors with poly-Si and poly-Si/sub 0.7/Ge/sub 0.3/ gate material

Experimental examination of physical model for direct tunneling current in unstressed/stressed ultrathin gate oxides

Photo-carrier generation as the origin of Fowler-Nordheim-induced substrate hole current in thin oxides

Toward scientific manufacturing

Analysis of SRAM bit failure at high frequency operation

Intra-field gate CD variability and its impact on circuit performance

An in-line contact and via hole inspection method using electron beam compensation current

Tools for non-invasive optical characterization of CMOS circuits

A manufacturable multiple gate oxynitride thickness technology for system on a chip

Silicide induced pattern density and orientation dependent transconductance in MOS transistors

Improved PMOSFET short-channel performance using ultra-shallow Si/sub 0.8/Ge/sub 0.2/ source/drain extensions

A novel atomic layer doping technology for ultra-shallow junction in sub-0.1 /spl mu/m MOSFETs

70 nm MOSFET with ultra-shallow, abrupt, and super-doped S/D extension implemented by laser thermal process (LTP)

Heavily doped and extremely shallow junctions on insulator by SONCTION (SilicON Cut-off juncTION) process

A new substrate engineering for the formation of empty space in silicon (ESS) induced by silicon surface migration

Issues in modeling small devices

Explaining the dependences of electron and hole mobilities in Si MOSFET's inversion layer

Compact and accurate quantum correction for MOS device simulator

Quantum mechanical enhancement of the random dopant induced threshold voltage fluctuations and lowering in sub 0.1 micron MOSFETs

Statistical pn junction leakage model with trap level fluctuation for Tref (refresh time)-oriented DRAM design

Physics-based analysis of RF performance of small geometry MOSFETs: methodology and application to the evaluation of the effects of scaling

Performance limits of silicon MOSFET's

12 ps implanted base silicon bipolar technology

A 0.2-/spl mu/m self-aligned SiGe HBT featuring 107-GHz f/sub max/ and 6.7-ps ECL

Modular integration of high-performance SiGe:C HBTs in a deep submicron, epi-free CMOS process

Very low cost graded SiGe base bipolar transistors for a high performance modular BiCMOS process

A 0.18 /spl mu/m 90 GHz f/sub T/ SiGe HBT BiCMOS, ASIC-compatible, copper interconnect technology for RF and microwave applications

SiGe profile design tradeoffs for RF circuit applications

High performance 0.15 /spl mu/m self-aligned SiGe p-MOS-MODFET's with SiN gate dielectric

High-efficiency uni-traveling-carrier photodiode with an integrated total-reflection mirror

Improved ultraviolet quantum efficiency using a transparent recessed window AlGaN/GaN heterojunction p-i-n photodiode

Multiple-color GaAs/AlGaAs superlattice infrared photodetector controlled by the polarity and magnitude of the bias voltage

Patterned 1.54 /spl mu/m vertical cavity laser with mismatched defect-free mirrors

Mid-IR type-II interband cascade lasers based on InAs/GaInSb heterostructures

Photon recycling semiconductor light emitting diode

Advanced interconnect schemes towards 0.1 /spl mu/m

Full-0.56 /spl mu/m pitch copper interconnects for a high performance 0.15-/spl mu/m CMOS logic device

0.5-/spl mu/m-pitch copper-dual-damascene metallization using organic SOG (k=2.9) for 0.18-/spl mu/m CMOS applications

Copper dual damascene interconnects with low-K (K/sub eff/<3.0) dielectrics using FLARE/sup TM/ and an organo-silicate hard mask

Chip-level performance improvement using triple damascene wiring design concept for 0.13 /spl mu/m CMOS devices

On-chip interconnect evaluation on delay time increase by crosstalk

Layered Ta-nitrides (LTN) barrier film by power swing sputtering (PSS) technique for MOCVD-Cu damascene interconnects

CMOS device technology toward 50 nm region-performance and drain architecture

Optimized halo structure for 80 nm physical gate CMOS technology with indium and antimony highly angled ion implantation

An 80 nm dual-gate CMOS with shallow extensions formed after activation annealing and SALICIDE

50 nm gate-length CMOS transistor with super-halo: design, process, and reliability

Effect of <100> channel direction for high performance SCE immune pMOSFET with less than 0.15 /spl mu/m gate length

Polysilicon gate with depletion-or-metallic gate with buried channel: what evil worse ?

A 0.13 /spl mu/m CMOS technology integrating high-speed and low-power/high-density devices with two different well/channel structures

Ultra-low leakage 0.16 /spl mu/m CMOS for low-standby power applications

A highly manufacturable 0.18 /spl mu/m generation logic technology

High performance 0.18 /spl mu/m SOI CMOS technology

1 GHz microprocessor integration with high performance transistor and low RC delay

Low actuation voltage RF MEMS switches with signal frequencies from 0.25 GHz to 40 GHz

A micro-electro-mechanically (MEM) switched microstrip ring resonator

A low-voltage rotary actuator fabricated using a five-level polysilicon surface micromachining technology

Surface/bulk micromachining (SBM) process and deep trench oxide isolation method for MEMS

Very large current density from carbon nanotube field emitters

Co-silicide formation on silicon FEAs from Co, Co/Ti and Ti/Co layers

An anode hole injection percolation model for oxide breakdown-the "doom's day" scenario revisited

A physics-based, unified gate-oxide breakdown model

Analysis of trap-assisted conduction mechanisms through silicon dioxide films using quantum yield

Monte Carlo simulation of quantum yields exceeding unity as a probe of high-energy hole scattering rates in Si

Low voltage tunneling in ultra-thin oxides: a monitor for interface states and degradation

Direct tunneling current model for circuit simulation

A novel hot carrier mechanism: band-to-band tunneling hole induced bipolar hot electron (BBHBHE)

Light emission from MOS tunnel diodes

Light emission and detection by metal oxide silicon tunneling diodes

Monolithic high-Q overhang inductors fabricated on silicon and glass substrates

Integration of high-Q inductors in a latch-up resistant CMOS technology

Reference SAW oscillator on quartz-on-silicon (QoS) wafer for polylithic integration of true single chip radio

CoSi/sub 2/ integrated fuses on poly silicon for low voltage 0.18 /spl mu/m CMOS applications

InP-based high-speed electronics

A DC-3 GHz cryogenic AlGaAs/GaAs HBT low noise MMIC amplifier with 0.15 dB noise figure

69 GHz frequency divider with a cantilevered base InP DHBT

Metamorphic In/sub 0.52/Al/sub 0.48/As/In/sub 0.53/Ga/sub 0.47/As HEMTs on GaAs substrate with f/sub T/ over 200 GHz

Low temperature (Ba,Sr)TiO/sub 3/ capacitor process integration (LTB) technology for gigabit scaled DRAMs

Development of Ru/Ta/sub 2/O/sub 5//Ru capacitor technology for giga-scale DRAMs

Advanced amorphous dielectrics for embedded capacitors

A hydrogen barrier interlayer dielectric with a SiO/sub 2//SiON/SiO/sub 2/ stacked film for logic-embedded FeRAMs

Advanced thermally stable silicide S/D electrodes for high-speed logic circuits with large-scale embedded Ta/sub 2/O/sub 5/-capacitor DRAMs

Level-specific strategy of KrF microlithography for 130 nm DRAMs

Extraction of the gate oxide thickness of N- and P-Channel MOSFETs below 20 /spl Aring/ from the substrate current resulting from valence-band electron tunneling

Improvement of direct-tunneling gate leakage current in ultra-thin gate oxide CMOS with TiN gate electrode using non-doped selective epitaxial Si channel technique

Investigation of intrinsic transistor performance of advanced CMOS devices with 2.5 nm NO gate oxides

NMOS drive current reduction caused by transistor layout and trench isolation induced stress

Analysis and control of hysteresis in PD/SOI CMOS

Actively biased p-channel MOSFET studied with scanning capacitance microscopy

1/f noise characterization of deep sub-micron dual thickness nitrided gate oxide n- and p-MOSFETs

Integration and design issues in combining very-high-speed silicon-germanium bipolar transistors and ULSI CMOS for system-on-a-chip applications

'System on a chip' technology platform for 0.18 /spl mu/m digital, mixed signal and eDRAM applications

RF potential of a 0.18-/spl mu/m CMOS logic technology

A 0.16 /spl mu/m modular BiCMOS (COM2-BiCMOS) technology for RF communication ICs

Impact of interconnect capacitance reduction on RF-Si device performance

Performance limits in visible and infrared imager sensors

A low dark current double membrane poly-Si FT-technology for 2/3 inch 6M pixel CCD imagers

A high speed CMOS imager acquiring 5000 frames/sec

Intelligent image sensor chip with three dimensional structure

New LV-BPD (low voltage buried photo-diode) for CMOS imager

A new sensor structure and fabrication process for a single-chip fingerprint sensor/identifier LSI

A fast and accurate computation of interconnect capacitance

Ultra low capacitance measurements in multilevel metallisation CMOS by using a built-in electron-meter

Line inductance extraction and modeling in a real chip with power grid

Characterization of crosstalk-induced noise for 0.18 /spl mu/m CMOS technology with 6-level metallization using time domain reflectometry and S-parameters

A two-dimensional low pass filter model for die-level topography variation resulting from chemical mechanical polishing of ILD films

A novel approach to simulate the effect of optical proximity on MOSFET parametric yield

Ultra-thin body SOI MOSFET for deep-sub-tenth micron era

A Direct Tunneling Memory (DTM) utilizing novel floating gate structure

High Al-content AlGaN/GaN HEMTs on SiC substrates with very high power performance

Very high performance 50 nm CMOS at low temperature

Ultra-low contact resistance for deca-nm MOSFETs by laser annealing

High performance strained-Si p-MOSFETs on SiGe-on-insulator substrates fabricated by SIMOX technology

0.1-/spl mu/m CMOS technology for high-speed logic and system LSIs with SiO/SiN/poly-Si/W gate-system

Electrical properties of submicron (/spl ges/0.13 /spl mu/m/sup 2/) Ir/PZT/Ir capacitors formed on W plugs

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)

International Electron Devices Meeting. IEDM Technical Digest

International Electron Devices Meeting. Technical Digest

Proceedings of International Electron Devices Meeting

Proceedings of 1994 IEEE International Electron Devices Meeting

Proceedings of IEEE International Electron Devices Meeting

1992 International Technical Digest on Electron Devices Meeting

International Electron Devices Meeting 1991 [Technical Digest]

International Technical Digest on Electron Devices

International Technical Digest on Electron Devices Meeting

Technical Digest., International Electron Devices Meeting

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