NDLI: A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects

Content Provider	IEEE Xplore Digital Library
Author	Ravindra, J.V.R. Srinivas, M.B.
Copyright Year	2007
Description	Author affiliation: Center for VLSI & Embedded Syst. Technol., Int. Inst. of Inf. Technol., Hyderabad, India (Ravindra, J.V.R.; Srinivas, M.B.)
Abstract	For optimizations like placement, interconnect synthesis and static timing analysis, efficient interconnect delay computation is critical for RC networks. Because of its simple closed form and fast evaluation, the Elmore delay model has been widely used. The other delay metrics PRIMO and H-gamma match the first three circuit moments to the probability density function (PDF) of a Gamma statistical distribution. Although these methods demonstrate impressive accuracy compared to other delay metrics, their implementations tend to be challenging. In this paper simple and efficient two-parameter analytic expressions for both delay and slew, based on Erlang distribution (ERD) function, are presented under process variations. The effectiveness of the proposed metrics for RC trees is proved through experimental results.
Starting Page	325
Ending Page	330
File Size	745764
Page Count	6
File Format	PDF
ISBN	9780769529783
DOI	10.1109/DSD.2007.4341488
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-08-29
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay estimation Delay effects Very large scale integration Integrated circuit interconnections Circuit synthesis Network synthesis Timing Computer networks Probability density function Statistical distributions
Content Type	Text
Resource Type	Article

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