NDLI: High-resolution temperature sensing with source-gated transistors

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2015 73rd Annual Device Research Conference (DRC)

72nd Device Research Conference

71st Device Research Conference

70th Device Research Conference

69th Device Research Conference

Technical program committee

Schedule of events

Table of contents

Plenary session

Soft, curvilinear semiconductor devices for bio-integrated electronics

Devices for high performance computing beyond 14nm node - is there anything other than Si?

The latest performance of GaN-based nonpolar and semipolar emitting devices

Ultra-thin compound semiconductor on insulator (XOI) for MOSFETs and TFETs

Experimental investigation of scalability and transport in In0.7Ga0.3As multi-gate quantum well FET (MuQFET)

60 nm gate length Al2O3 / In0.53Ga0.47As gate-first MOSFETs using InAs raised source-drain regrowth

15 nm diameter InAs nanowire MOSFETs

The nanoelectronic modeling tool NEMO 5: Capabilities, validation, and application to Sb-heterostructures

Experimental determination of dominant scattering mechanisms in scaled InAsSb quantum well

Graphene [Session content]

Integration of high quality top-gated graphene field effect devices on 150 mm substrate

Complementary-type graphene inverters operating at room-temperature

Gate capacitance scaling and graphene field-effect transistors with ultra-thin top-gate dielectrics

Synthesis and applications of graphene for flexible electronics

Sub-10 nm epitaxial graphene nanoribbon FETs

Effect of oxide thickness scaling on self-heating in graphene transistors

Graphene quantum capacitance varactors for wireless sensing applications

Effects of heavily doped source on the subthreshold characteristics of nanowire tunneling transistors

Spatially resolved photovoltaic performance of axial GaAs nanowire pn-diodes

Low loss AlInN/GaN Monolithic Microwave Integrated Circuit switch

High-mobility organic thin-film transistors with photolithographically patterned top contacts

High breakdown voltage ZnMgO/In-Ga-Zn-O heterostructure transistors

High-resolution temperature sensing with source-gated transistors

Voltage-controlled spin-wave-based logic gate

Effect of disorder on superfluidity in double layer graphene

Dual Pillar Spin Transfer Torque MRAM with tilted magnetic anisotropy for fast and error-free switching and near-disturb-free read operations

Giant magnetoelectric effect in nanofabricated Pb(Zr0.52Ti0.48)O3-Fe85B5Si10 cantilevers and resonant gate transistors

Observation of trap-assisted steep sub-threshold swing in schottky source/drain Al2O3/InAlN/GaN MISHEMT

Towards electronics at 1000 °C

Bias temperature stress analysis of ZnO thin film transistors with HfO2 gate dielectrics

Carbon nanotube purified ink-based printed thin film transistors: Novel approach in controlling the electrical performance

Monolayer MoS2 transistors - ballistic performance limit analysis

RF performance projections for 2D graphene transistors: Role of parasitics at the ballistic transport limit

High performance N- and P-type gate-all-around nanowire MOSFETs fabricated on bulk Si by CMOS-compatible process

The effect of field effect device channel dimensions on the effective mobility of graphene

Top-gated single-electron transistor in germanium nanowires

Reliability of ambipolar switching poly-Si diodes for cross-point memory applications

Electrochemical supercapacitor based on flexible pillar graphene nanostructures

“Zero” drain-current drift of inversion-mode NMOSFET on InP (111)A surface

Improvement of efficiency in inverted bottom-emission white OLEDs by doping the hole transport layer

Vertical organic field-effect transistor array fabrication based on laser holography lithography process

Ambipolar nano-crystalline-silicon TFTs with submicron dimensions and reduced threshold voltage shift

Monolithically grown InxGa1−xAs nanowire on silicon tandem solar cells with high efficiency

3D simulation of electrical characteristic fluctuation induced by interface traps at Si/high-к oxide interface and random dopants in 16-nm-Gate CMOS devices

Creating dynamic nanowire devices using wrapped gates

InAlAs/InGaAs metamorphic HEMT and MOS-HEMT with regrown Source/Drain by MOCVD

Numerical study of electronic transport through bilayer graphene nanoribbons

Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier

Orientation dependent complex bandstructure of Si1−xGex alloys

Towards planar GaAs nanowire array high electron mobility transistor

Interface states at high- к /InGaAs interface: H2O vs. O3 based ALD dielectric

C-V measurements of single vertical nanowire capacitors

Barrier height, interface charge & tunneling effective mass in ALD Al2O3/AlN/GaN HEMTs

Graphene field-effect transistors using large-area monolayer graphene grown by chemical vapor deposition on Co thin films

Modeling of dielectric breakdown-induced time-dependent STT-MRAM performance degradation

Introduction of ALD Beryllium oxide gate dielectric for III–V MOS devices

Transport properties of CVD-grown graphene nanoribbon field-effect transistors

Protein nanopore-gated bio-transistor for membrane ionic current recording

Tunnel FET-based pass-transistor logic for ultra-low-power applications

Metal/III–V effective barrier height tuning using ALD high-κ dipoles

Intrinsic DC operation and performance potential of 50nm gate length hydrogen-terminated diamond field effect transistors

Improvement of fT in InAl(Ga)N barrier HEMTs by plasma treatments

Scaling behavior and velocity enhancement in self-aligned N-polar GaN/AlGaN HEMTs with maximum fT of 163 GHz

Fermi-level pinning at metal/antimonides interface and demonstration of antimonides-based metal S/D Schottky pMOSFETs

Uniaxially tensile strained accumulation-mode gate-all-around Si nanowire nMOSFETs

Spintronics search engines

Low frequency transconductance and output resistance dispersion of epitaxial graphene nanoribbon-based field effect transistors

InAs/SiGe on Si nanowire tunneling field effect transistors

Electrical measurement of the spin Hall effects in Fe/InxGa1−xAs heterostructures

Simultaneous spin and charge transport in gated Si devices

Unidirectional information transfer with cascaded All Spin Logic devices: A Ring Oscillator

Proposal for piezoelectric-ferromagnet bilayer based microwave oscillators without any external magnetic field or spin transfer torque

Orthogonal spin transfer MRAM

Thermal effects and instability in unipolar resistive switching devices

A hybrid ferroelectric and charge nonvolatile memory

Spin-torque switchable perpendicular magnetic junctions for solid-state memory

Alternative transistor concepts

Combinational and sequential logic with transistors based on individual carbon nanotubes

Comparative study of fabricated junctionless and inversion-mode nanowire FETs

Fabrication of vertical InAs-Si heterojunction tunnel field effect transistors

Challenges for post-CMOS devices & architectures

Correlated oxide phase transition switch: A paradigm in electron devices

Lateral gate suspended-body carbon nanotube field-effect-transistors with sub-100nm air gap by precise positioning method

Si-based tunnel field-effect transistors for low-power nano-electronics

Compact model and performance estimation for tunneling nanowire FET

Using dimensionality to achieve a sharp tunneling FET (TFET) turn-on

Investigation on superlattice heterostructures for steep-slope nanowire FETs

Self-aligned gate nanopillar In0.53Ga0.47As vertical tunnel transistor

Self-aligned InAs/Al0.45Ga0.55Sb vertical tunnel FETs

P-type tunneling FET on Si (110) substrate with anisotropic effect

Wide bandgap [session program]

Anomalous output conductance in N-polar GaN-based MIS-HEMTs

Normally-off gate-recessed AlGaN/GaN-on-Si hybrid MOS-HFET with Al2O3 gate dielectric

N-Polar AlGaN/GaN MIS-HEMTs on SiC with a 16.7 W/mm power density at 10 GHz using an Al2O3 based etch stop technology for the gate recess

Total GaN solution to electrical power conversion

First AlN/GaN HEMTs power measurement at 18 GHz on Silicon substrate

Enhanced mobility for MOCVD grown AlGaN/GaN HEMTs on Si substrate

High performance GaN-on-Si power switch: Role of substrate bias in device characteristics

High mobility strained p-channel germanium quantum well field effect transistor for low power (Vcc = 0.5 V) III–V CMOS applications

Performance enhancement of GaAs UTB pFETs by strain, orientation and body thickness engineering

Highly-strained SGOI p-channel MOSFETs fabricated by applying Ge condensation technique to strained-SOI substrates

Hole mobility enhancement in uniaxially strained SiGe FINFETs: Analysis and prospects

Thin-film devices

Defect analysis of roll-to-roll SAIL manufactured flexible display backplanes

Indium-free transparent thin film transistors based on nanocrystalline ZnO

Circuit applications based on solution-processed zinc-tin oxide TFTs

Aluminum top-gate ZnO nanowire transistors with improved transconductance

Optoelectronic devices

Monolithic integration of CMOS and nanophotonic devices for massively parallel optical interconnects in supercomputers

Electrical pumped integrated III/V laser lattice-matched to a Silicon substrate

Lateral carrier injection with n-type modulation-doped quantum wells in VCSELs

Near UV AlGaN-cladding free nonpolar InGaN/GaN laser diodes

RIE lag directional coupler based integrated InGaAsP/InP ring mode-locked laser

Integrated non-III-nitride/III-nitride tandem solar cell

High speed devices

N-polar GaN HEMTs with fmax > 300 GHz using high-aspect-ratio T-gate design

1.0 THz fmax InP DHBTs in a refractory emitter and self-aligned base process for reduced base access resistance

Effect of optical phonon scattering on the performance limits of ultrafast GaN transistors

Device scaling technologies for ultra-high-speed GaN-HEMTs

Trap-related delay analysis of self-aligned N-polar GaN/InAlN HEMTs with record extrinsic gm of 1105 mS/mm

130nm InP DHBTs with ft >0.52THz and fmax >1.1THz

Conference at a glance

Addendum - UPDATED - 69th Device Research Conference Technical Program

Self-aligned gate-last surface channel $In_{0.53}Ga_{0.47}As$ MOSFET with selectively regrown source and drain contact layers

Vertically scaled 5 nm GaN channel enhancement-mode N-polar GaN MOS-HFET with 560 mS/mm $g_{m}$ and 0.76 Ω-mm $R_{on}$

Low-threshold room-temperature lasing in bottom-up photonic crystal cavities formed by patterned III-V nanopillars

III-nitride tunnel diodes with record forward tunnel current density

68th Device Research Conference

2009 Device Research Conference

2008 Device Research Conference

2007 65th Annual Device Research Conference

2006 64th Device Research Conference

63rd Device Research Conference Digest, 2005. DRC '05.

Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.

61st Device Research Conference. Conference Digest (Cat. No.03TH8663)

60th DRC. Conference Digest Device Research Conference

Device Research Conference. Conference Digest (Cat. No.01TH8561)

58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)

1999 57th Annual Device Research Conference Digest (Cat. No.99TH8393)

56th Annual Device Research Conference Digest (Cat. No.98TH8373)

1997 55th Annual Device Research Conference Digest

1996 54th Annual Device Research Conference Digest

1995 53rd Annual Device Research Conference Digest

52nd Annual Device Research Conference

51st Annual Device Research Conference

50th Annual Device Research Conference

[1991] 49th Annual Device Research Conference Digest

High-resolution temperature sensing with source-gated transistors

Content Provider	IEEE Xplore Digital Library
Author	Sporea, R.A. Shannon, J.M. Silva, S.R.P.
Copyright Year	2011
Description	Author affiliation: Advanced Technology Institute, FEPS, University of Surrey, Guildford, GU2 7XH, U.K. (Sporea, R.A.; Shannon, J.M.; Silva, S.R.P.)
Abstract	Source-gated transistors (SGTs) [1] are three-terminal devices in which the current is controlled by a potential barrier at the source. The gate voltage is used primarily to modulate the effective height of the source barrier. These devices have a number of operational advantages over conventional field-effect transistors, including a potentially much smaller saturation voltage and very low output conductance in saturation, which lead to low power operation and high intrinsic gain [2].
Starting Page	61
Ending Page	62
File Size	586474
Page Count	2
File Format	PDF
ISBN	9781612842431
ISSN	15483770
e-ISBN	9781612842448
e-ISBN	9781612842424
DOI	10.1109/DRC.2011.5994463
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Silicon compounds Insulators Glass Windows Sensors
Content Type	Text
Resource Type	Article

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