NDLI: Energy-Efficient FPGA Interconnect Design

Content Provider	IEEE Xplore Digital Library
Author	Meijer, M. Krishnan, R. Bennebroek, M.
Copyright Year	2006
Description	Author affiliation: Philips Res. Labs., Eindhoven (Meijer, M.)
Abstract	Despite recent advances in FPGA devices and embedded cores, their deployment in commercial products remains rather limited due to practical constraints on, for example, cost, size, performance, and/or energy consumption. In this paper, we address the latter bottleneck and propose a novel FPGA interconnect architecture that reduces energy consumption without sacrificing performance and size. It is demonstrated that the delay of a full-swing, fully-buffered interconnect architecture can be matched by a low-swing solution that dissipates significantly less power and contains a mix of buffer and pass-gate switches. The actual energy savings depend on the specifics of the interconnect design and applications involved. For the considered fine-grain FPGA example, energy savings are observed to range from a factor 4.7 for low-load critical nets to a factor 2.8 for high-load critical nets. The results are obtained from circuit simulations in a 0.13mum CMOS technology for various benchmarks
Starting Page	1
Ending Page	6
File Size	899343
Page Count	6
File Format	PDF
ISBN	3981080114
DOI	10.1109/DATE.2006.243746
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-03-06
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Energy efficiency Field programmable gate arrays Integrated circuit interconnections Energy consumption CMOS technology Costs Delay Switches Circuit simulation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Minimizing FPGA interconnect delays

Energy efficient fine-grain reconfigurable hardware

Collaborative Routing Architecture for FPGA

FPGA interconnect design using logical effort

Exploring technology alternatives for nano-scale FPGA interconnects

The impact of copy-elements on QDI asynchronous FPGA interconnect structure

The design of a low energy FPGA

Circuit design, transistor sizing and wire layout of FPGA interconnect

Asynchronous FPGA architecture with distributed control

Energy-Efficient FPGA Interconnect Design

Similar Documents

Minimizing FPGA interconnect delays

Energy efficient fine-grain reconfigurable hardware

Collaborative Routing Architecture for FPGA

FPGA interconnect design using logical effort

Exploring technology alternatives for nano-scale FPGA interconnects

The impact of copy-elements on QDI asynchronous FPGA interconnect structure

The design of a low energy FPGA

Circuit design, transistor sizing and wire layout of FPGA interconnect

Asynchronous FPGA architecture with distributed control

Energy-Efficient FPGA Interconnect Design