NDLI: Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications

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Proceedings of the Design Automation & Test in Europe Conference

Volume 2 - 2006

Volume 1 - 2006

Table of contents

Contributor Listings

Reviewer and referee listings

Best Paper Awards

Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip

Efficient Link Capacity and QoS Design for Network-on-Chip

Supporting Task Migration in Multi-Processor Systems-on-Chip: A Feasibility Study

Time Domain Model Order Reduction by Wavelet Collocation Method

Large power grid analysis using domain decomposition

Analysis and Modeling of Power Grid Transmission lines

A Logarithmic Full-Chip Thermal Analysis Algorithm Based on Multi-Layer Green’s Function

Large Scale RLC Circuit Analysis Using RLCG-MNA Formulation

Soft Delay Error Analysis in Logic Circuits

A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap

Analysis of the impact of bus implemented EDCs on on-chip SSN

Optimal Periodic Testing of Intermittent Faults In Embedded Pipelined Processor Applications

Berger Code-Based Concurrent Error Detection in Asynchronous Burst-Mode Machines

Two-Phase Resonant Clocking for Ultra-Low-Power Hearing Aid Applications

A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes

A Single Photon Avalanche Diode Array Fabricated in Deep-Submicron CMOS Technology

MATLAB/Simulink for Automotive Systems Design

Model-Based Development of In-Vehicle Software

Model-Based Testing of Automotive Electronics

Designing signal processing systems for FPGAs

From UML/SysML to Matlab/Simulink: Current State and Future Perspectives

An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles

Exploiting TLM and Object Introspection for System-Level Simulation

Efficient Assertion Based Verification using TLM

Constructing Portable Compiled Instruction-set Simulators-An ADL-driven Approach

A Methodology for Mapping Multiple Use-Cases onto Networks on Chips

Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness

A Low Complexity Heuristic for Design of Custom Network-on-Chip Architectures

A dynamically reconfigurable packet-switched network-on-chip

Arbitrary Design of High Order Noise Transfer Function for A Novel Class of Reduced-Sample-Rate Sigma-Delta-Pipeline ADCs

Systematic and optimal design of CMOS two-stage opamps with hybrid cascode compensation

Systematic stability-analysis method for analog circuits

ALAMO: An Improvedσ-Space Based Methodology for Modeling Process Parameter Variations in Analog Circuits

A Synthesis Tool for Power-Efficient Base-Band Filter Design

An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits

Low-Cost and Highly Reliable Detector for Transient and Crosstalk Faults Affecting FPGA Interconnects

Evaluating Coverage of Error Detection Logic for Soft Errors using Formal Methods

Soft-error classification and impact analysis on real-time operating systems

40Gbps De-Layered Silicon Protocol Engine for TCP Record

A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applications

Disclosing the LDPC code decoder design space

Automating Processor Customisation: Optimised Memory Access and Resource Sharing

Automatic Identification of Application-Specific Functional Units with Architecturally Visible Storage

Combining Algorithm Exploration with Instruction Set Design: A Case Study in Elliptic Curve Cryptography

Simultaneously Improving Code Size, Performance, and Energy in Embedded Processors

Quantitative Analysis of Transaction Level Models for the AMBA Bus

Combining Simulation and Formal Methods for System-Level Performance Analysis

Formal Performance Analysis and Simulation of UML/SysML Models for ESL Design

Performance Evaluation for System-on-Chip Architectures using Trace-based Transaction Level Simulation

Is“Network” the Next “Big Idea” in Design?

Verifying analog oscillator circuits using forward/backward abstraction refinement

Efficient AC Analysis of Oscillators using Least-Squares Methods

Double-Strength CAFFEINE: Fast Template-Free Symbolic Modeling of Analog Circuits via Implicit Canonical Form Functions and Explicit Introns

Top-Down Heterogeneous Synthesis of Analog and Mixed-Signal Systems

Nonlinear Model Order Reduction Using Remainder Functions

Efficient Temperature - Dependent Symbolic Sensitivity Analysis and Symbolic Performance Evaluation in Analog Circuit Synthesis

Hierarchy-Aware and Area-Efficient Test Infrastructure Design for Core-Based System Chips

Power Constrained and Defect-Probability Driven SoC Test Scheduling with Test Set Partitioning

Power-Constrained Test Scheduling for Multi-Clock Domain SoCs

Reuse-based test access and integrated test scheduling for network-on-chip

A Design for Failure Analysis (DFFA) Technique to Ensure Incorruptible Signatures

Test Generation for Combinational Quantum Cellular Automata (QCA) Circuits

Analysis and Synthesis of Quantum Circuits by Using Quantum Decision Diagrams

Droplet Routing in the Synthesis of Digital Microfluidic Biochips

Priority Scheduling in Digital Microfluidics-Based Biochips

A hybrid framework for design and analysis of fault-tolerant architectures

Optical Routing for 3D System-On-Package

Distributed Loop Controller Architecture for Multi-threading in Uni-threaded VLIW Processors

Compositional, efficient caches for a chip multi-processor

Efficient Design Space Exploration of High Performance Embedded Out-of-Order Processors

Application-Specific Reconfigurable XOR-Indexing to Eliminate Cache Conflict Misses

A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures

Compiler-driven FPGA-area allocation for reconfigurable computing

Temporal Partitioning for Image Processing Based on Time-Space Complexity in Reconfigurable Architectures

System-level Scheduling on Instruction Cell Based Reconfigurable Systems

DATE 2006 Special Session: DFM/DFY Design for Manufacturability and Yield - influence of process variations in digital, analog and mixed-signal circuit design

Systematic Methodology for Designing Reconfigurabl D S Modulator Topologies for Multimode Communication Systems

Double-Sampling Single-Loop Sigma-Delta Modulator Topologies for Broadband Applications

A 10-GHz 15-dB Four-Stage Distributed Amplifier in 0.18μm CMOS Process

Bootstrapped full-swing CMOS driver for low supply voltage operation

An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs

Timing-reasoning-based delay fault diagnosis

Multiple-Fault Diagnosis Based on Single-Fault Activation and Single-Output Observation

Software-Based Self-Test of Processors under Power Constraints

Diagnosis of Defects on Scan Enable and Clock Trees

Lock-Free Synchronization for Dynamic Embedded Real-Time Systems

Performance analysis of greedy shapers in real-time systems

Improved offset-analysis using multiple timing-references

Procrastinating voltage scheduling with discrete frequency sets

Communication and Co-Simulation Infrastructure for Heterogeneous System Integration

A SW performance estimation framework for early system-level-design using fine-grained instrumentation

A Unified System-Level Modeling and Simulation Environment for MPSoC design: MPEG-4 Decoder Case Study

Task-accurate performance modeling in SystemC for real-time multi-processor architectures

Distributed Object Models for Multi-Processor SoC’s, with Application to Low-power Multimedia Wireless Systems

Virtual Prototyping of Embedded Platforms for Wireless and Multimedia

Application Specific NoC Design

Automatic Insertion of Low Power Annotations in RTL for Pipelined Microprocessors

Power Analysis of Mobile 3D Graphics

Automatic Run-Time Selection of Power Policies for Operating Systems

Energy Reduction by Workload Adaptation in a Multi-Process Environment

Dynamic Bit-width Adaptation in DCT: Image Quality versus Computation Energy Trade-off

Bus Stuttering : An Encoding Technique to Reduce Inductive Noise in Off-Chip Data Transmission

Statistical timing analysis with path reconvergence and spatial correlations

Non-Gaussian Statistical Interconnect Timing Analysis

Cell Delay Analysis Based on Rate-of-Current Change

A practical method to estimate interconnect responses to variabilities

Panel: Test and Reliability Challenges in Automotive Microelectronics

Exploring Trade-off’s Between Centralized versus Decentralized Automotive Architectures Using a Virtual Integration Environment

Management of Complex Automotive Communication Networks

AutoVision - flexible processor architecture for video-assisted driving

Domain specific model driven design for automotive electronic control units

Electric and electronic vehicle architecture assessment

Automotive Semi-Conductor Trend & Challenges

A systematic IP and bus subsystem modeling for platform-based system design

Heterogeneous Behavioral Hierarchy for System Level Designs

Design with race-free hardware semantics

Comfortable Modeling of Complex Reactive Systems

Faster Exploration of High Level Design Alternatives using UML for Better Partitions

A design flow for configurable embedded processors based on optimized instruction set extension synthesis

Energy efficiency vs. programmability trade-off: architectures and design principles

Advanced receiver algorithms for MIMO wireless communications

Keynote: next generation architectures can dramatically reduce the 4G deployment cycle

Automatic ADL-based Operand Isolation for Embedded Processors

Power/Performance Hardware Optimization for Synchronization Intensive Applications in MPSoCs

An analytical state dependent leakage power model for FPGAs

Smart Bit-width Allocation for Low Power Optimization in a SystemC based ASIC Design Environment

Value-Based Bit Ordering for Energy Optimization of On-Chip Global Signal Buses

Modeling multiple input switching of CMOS gates in DSM technology using HDMR

A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits

Using conjugate symmetries to enhance gate-level simulations

HDL Models of Ferromagnetic Core Hysteresis Using Timeless Discretisation of the Magnetic Slope

An Improved RF Loopback for Test Time Reduction

Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking

Online RF Checkers for Diagnosing Multi-Gigahertz Automatic Test Boards on Low Cost ATE Platforms

Pseudorandom Functional BIST for Linear and Nonlinear MEMS

On-chip 8GHz Non-Periodic High-Swing Noise Detector

Battery-aware Code Partitioning for a Text to Speech System

Performance optimization for energy-aware adaptive checkpointing in embedded real-time systems

Software Annotations for Power Optimization on Mobile Devices

Dynamic partitioning of processing and memory resources in embedded MPSoC architectures

Activity Clustering for Leakage Management in SPMs

Adaptive Data Placement in an Embedded Multiprocessor Thread Library

COSMECA: Application Specific Co-Synthesis of Memory and Communication Architectures for MPSoC

Synthesis of Fault-Tolerant Schedules with Transparency/Performance Trade-offs for Distributed Embedded Systems

Communication architecture optimization: making the shortest path shorter in regular networks-on-chip

Buffer Space Optimisation with Communication Synthesis and Traffic Shaping for NoCs

Cooptimization of Interface Hardware and Software for I/O Controllers

HOT TOPIC: Cross Disciplinary Aspects (4G Wireless Special Day)

SoC–Fuelling the Hopes of the Mobile Industry

Integrated Data Relocation and Bus Reconfiguration for Adaptive System-on-Chip Platforms

FPGA Architecture Characterization for System Level Performance Analysis

Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications

Customization of application specific heterogeneous multi-pipeline processors

Impact of Bit-Width Specification on the Memory Hierarchy for a Real-Time Video Processing System

Efficient Factorization of DSP Transforms using Taylor Expansion Diagrams

Integrated Placement and Skew Optimization for Rotary Clocking

Associative Skew Clock Routing for Difficult Instances

Efficient Timing-Driven Incremental Routing for VLSI Circuits Using DFS and Localized Slack-Satisfaction Computations

Defect Tolerance of QCA Tiles

Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits

Novel designs for thermally robust coplanar crossing in QCA

Designing MRF based Error Correcting Circuits for Memory Elements

A Time-Triggered Ethernet (TTE) Switch

A Time Predictable Java Processor

Optimizing the Generation of Object-Oriented Real-Time Embedded Applications Based on the Real-Time Specification for Java

Quantifier structure in search based procedures for QBFs

Strong Conflict Analysis for Propositional Satisfiability

Equivalence verification of arithmetic datapaths with multiple word-length operands

4G applications, architectures, design methodology and tools for MPSoC

Thermal resilient bounded-skew clock tree optimization methodology

Exploring “temperature-aware” design in low-power MPSoCs

Adaptive Chip-Package Thermal Analysis for Synthesis and Design

On-chip Bus Thermal Analysis and Optimization

Ultralow Power Computing with Sub-threshold Leakage: A Comparative Study of Bulk and SOI Technologies

Low Power Synthesis of Dynamic Logic Circuits Using Fine-Grained Clock Gating

Enabling Fine-Grain Leakage Management by Voltage Anchor Insertion

Automated Exploration of Pareto-optimal Configurations in Parameterized Dynamic Memory Allocation for Embedded Systems

A Control Theoretic Approach to Run-Time Energy Optimization of Pipelined Processing in MPSoCs

3D Floorplanning with Thermal Vias

Timing-Driven Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization

Lens Aberration Aware Timing-Driven Placement

On test conditions for the detection of open defects

A compact model to identify delay faults due to crosstalk

Generation of Broadside Transition Fault Test Sets that Detect Four-Way Bridging Faults

Extraction of Defect Density and Size Distributions from Wafer Sort Test Results

An Interprocedural Code Optimization Technique for Network Processors Using Hardware Multi-Threading Support

An integrated scratch-pad allocator for affine and non-affine code

Dynamic Scratch-Pad Memory Management for Irregular Array Access Patterns

Restructuring Field Layouts for Embedded Memory Systems

Power-Aware Compilation for Embedded Processors with Dynamic Voltage Scaling and Adaptive Body Biasing Capabilities

Dynamic Code Overlay of SDF-Modeled Programs on Low-end Embedded Systems

optiMap: a tool for automated generation of NoC architectures using multi-port routers for FPGAs

Hardware Efficient Architectures for Eigenvalue Computation

Memory centric thread synchronization on platform FPGAs

A Parallel Configuration Model for Reducing the Run-Time Reconfiguration Overhead

Wireless Sensor Networks and Beyond

The Ultra Low-PowerWiseNET System

Fast-prototyping Using the BTnode Platform

Circuit-aware Device Design Methodology for Nanometer Technologies: A Case Study for Low Power SRAM Design

Architectural and Technology Influence on the Optimal Total Power Consumption

Reducing the Sub-threshold and Gate-tunneling Leakage of SRAM Cells using Dual-Vt and Dual-Tox Assignment

Exploiting Data-Dependent Slack Using Dynamic Multi-VDD to Minimize Energy Consumption in Datapath Circuits

On the Evaluation of Transactor-based Verification for Reusing TLM Assertions and Testbenches at RTL

Functional Verification Methodology Based on Formal Interface Specification and Transactor Generation

A Coverage Metric for the Validation of Interacting Processes

New Methods and Coverage Metrics for Functional Verification

Classification Trees for Random Tests and Functional Coverage

Efficient Test-Data Compression for IP Cores Using Multilevel Huffman Coding

Functional Constraints vs. Test Compression in Scan-Based Delay Testing

Concurrent Core Test for SOC Using Shared Test Set and Scan Chain Disable

Efficient Unknown Blocking Using LFSR Reseeding

Coverage Loss By Using Space Compactors in Presence of Unknown Values

Online energy-aware I/O device scheduling for hard real-time systems

Multiprocessor Synthesis for Periodic Hard Real-Time Tasks under a Given Energy Constraint

Scheduling under Resource Constraints using Dis-Equations

Scalable Performance-Energy Trade-off Exploration of Embedded Real-Time Systems on Multiprocessor Platforms

Building a Better Boolean Matcher and Symmetry Detector

Optimizing sequential cycles through Shannon decomposition and retiming

Efficient Incremental Clock Latency Scheduling for Large Circuits

Analyzing Timing Uncertainty in Mesh-based Clock Architectures

Platform-Based Design of Wireless Sensor Networks for Industrial Applications

An environment for controlled experiments with in-house sensor networks

Hogthrob: towards a sensor network infrastructure for sow monitoring (wireless sensor network special day)

Ultra-Efficient (Embedded) SOC Architectures based on Probabilistic CMOS (PCMOS) Technology

Minimizing Ohmic Loss and Supply Voltage Variation Using a Novel Distributed Power Supply Network

An Ultra Low-Power TLB Design

Determining the Optimal Timeout Values for a Power-Managed System based on the Theory of Markovian Processes: Offline and Online Algorithms

A Formal Model and Efficient Traversal Algorithm for Generating Testbenches for Verification of IEEE Standard Floating Point Division

On the relation between simulation-based and SAT-based diagnosis

An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration

Parallel co-simulation using virtual synchronization with redundant host execution

An Efficient and Portable Scheduler for RTOS Simulation and its Certified Integration to SystemC

Minimizing Test Power in SRAM through Reduction of Pre-charge Activity

Efficient On-line Interconnect Testing in FPGAs with Provable Detectability for Multiple Faults

A concurrent testing method for NoC switches

A secure Scan Design Methodology

RAS-NANO: A Reliability-Aware Synthesis Framework for Reconfigurable Nanofabrics

Layout Driven Data Communication Optimization for High Level Synthesis

Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits

Automatic generation of operation tables for fast exploration of bypasses in embedded processors

High Level Synthesis of Higher Order Continuous Time State Variable Filters with Minimum Sensitivity and Hardware Count

Disjunctive Image Computation for Embedded Software Verification

Distance-Guided Hybrid Verification with GUIDO

What lies between Design Intent Coverage and Model Checking?

On the Numerical Verification of Probabilistic Rewriting Systems

Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks

Tutorial And Panel Session Low-Power Design Tools: Are EDA Vendors Taking this Matter Seriously?

Formal Verification of SystemC Designs Using a Petri-Net Based Representation

Monolithic Verification of Deep Pipelines with Collapsed Flushing

Functional Test Generation using Property Decompositions for Validation of Pipelined Processors

Proven correct monitors from PSL specifications

Space of DRAM Fault Models and Corresponding Testing

Automatic March Tests Generations for Static Linked Faults in SRAMs

Test Compaction for Transition Faults under Transparent-Scan

Test Set Enrichment using a Probabilistic Fault Model and the Theory of Output Deviations

Vulnerability Analysis of L2 Cache Elements to Single Event Upsets

Area-Efficient Error Protection for Caches

Microarchitectural Floorplanning Under Performance and Thermal Tradeoff

Optimizing High Speed Arithmetic Circuits Using Three-Term Extraction

Efficient Minimization of Fully Testable 2-SPP Networks

Pre-synthesis Optimization of Multiplications to Improve Circuit Performance

Crosstalk-aware Domino Logic Synthesis

TRAIN: A Virtual Transaction Layer Architecture for TLM-based HW/SW Codesign of Synthesizable MPSoC

Configurable Multiprocessor Platform with RTOS for Distributed Execution of UML 2.0 Designed Applications

ASIP-Based Multiprocessor SoC Design for Simple and Double Binary Turbo Decoding

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Proceedings Design, Automation and Test in Europe

Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications

Content Provider	IEEE Xplore Digital Library
Author	Bartzas, A. Mamagkakis, S. Pouiklis, G. Atienza, D. Catthoor, F. Soudris, D. Thanailakis, A.
Copyright Year	2006
Description	Author affiliation: VLSI Design & Testing Center, Democritus Univ., Xanthi (Bartzas, A.; Mamagkakis, S.; Pouiklis, G.)
Abstract	Network applications are becoming increasingly popular in the embedded systems domain requiring high performance, which leads to high energy consumption. In networks is observed that due to their inherent dynamic nature the dynamic memory subsystem is a main contributor to the overall energy consumption and performance. This paper presents a new systematic methodology, generating performance-energy trade-offs by implementing dynamic data types (DDTs), targeting network applications. The proposed methodology consists of: (i) the application-level DDT exploration; (ii) the network-level DDT exploration; and (iii) the Pareto-level DDT exploration. The methodology, supported by an automated tool, offers the designer a set of optimal dynamic data type design solutions. The effectiveness of the proposed methodology is tested on four representative real-life case studies. By applying the second step, it is proved that energy savings up to 80% and performance improvement up to 22% (compared to the original implementations of the benchmarks) can be achieved. Additional energy and performance gains can be achieved and a wide range of possible trade-offs among our Pareto-optimal design choices are obtained, by applying the third step. We achieved up to 93% reduction in energy consumption and up to 48% increase in performance
File Size	756528
File Format	PDF
ISBN	3981080114
DOI	10.1109/DATE.2006.244093
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-03-06
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Energy consumption Embedded system Wireless networks Telecommunication traffic Runtime Performance evaluation Very large scale integration Large scale integration Benchmark testing Performance gain
Content Type	Text
Resource Type	Article

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