NDLI: Alleviating routing congestion by combining logic resynthesis and linear placement

Please wait, while we are loading the content...

1993 European Conference on Design Automation with the European Event in ASIC Design

Specification and verification of system-level hardware designs using time diagrams

Systolic VLSI implementations of a Galois field arithmetic algorithms

An ASIC macro cell multiplier for complex numbers

Design of a discrete cosine transform circuit using the residue number system

Alleviating routing congestion by combining logic resynthesis and linear placement

Technology decomposition using optimal alphabetic trees

OPTIMOS: A branch-level digital circuit optimizer

An approach to scheduling and allocation using regularity extraction

Heuristic techniques for the synthesis of complex functional units

Module selection and scheduling using unrestricted libraries

A digital phase locked loop for power conversion ASICs

A sea-of-gates-based, 10 MIPS 16-bit RISC processor testbed for failsafe applications

A design methodology achieving fast development cycles for complex VLSI architectures

Practical generalizations of asynchronous state machines

Synthesis and optimization of asynchronous controllers based on extended lock graph theory

Functional timing analysis using ATPG

Effective march algorithms for testing single-order addressed memories

Multiple observation time single reference test generation using synchronizing sequences

Test time reduction in scan designed circuits

ASIC implementation of complex image processing algorithms using silicon compilation techniques [for biomedical application]

Strategies for development and modelling of VHDL based macrocell library

CATALYST: A highly flexible CAD tool for architecture-level design and analysis of data converters

GENRIF: An integrated VLSI FIR filter compiler

A skew assumption logic simulation technique for potential spike detection

A new method of identifying critical paths for performance optimization

A new accurate and hierarchical timing analysis approach

CHAN: An efficient critical path analysis algorithm

Architectural-level fault simulation using symbolic data

Using circuit hierarchy for fault simulation in combinational and sequential circuits

Testability measures combining probablistic and sampling techniques

Circuit delay optimization as a multiple choice linear knapsack program

Cross-talk extraction from mask layout

Results of analyzing VLSI interconnect structures by a methodology based on mixed frequency-time domain

Relative location assignment for repetitive schedules

Scheduling algorithm in data path synthesis using the Tabu search technique

DLS: A scheduling algorithm for high-level synthesis in VHDL

Multi-level logic optimization based on pseudo maximum sets of permissible functions

Coherent optimization strategies for multilevel synthesis

Multi-level logic optimization by redundancy addition and removal

Circuit activity driven multilevel logic optimization for low power reliable operation

Power estimation for high level synthesis

A novel approach to cost-effective estimate of power dissipation in CMOS ICs

PRITI: Estimation of maximal currents and current derivatives in complex CMOS circuits using activities waveforms

Simulation and reduction of CMOS power dissipation at logic level

A systematic approach to defining the structure of a test suite for the NELSIS IC design system

Automatically updating technology dependent information in design automation

Rule-driven EDIF reference solving

An algorithm for partitioning of application specific systems

Technology mapping algorithms for NORA dynamic logic circuits

Technology mapping of mixed polarity Reed-Muller representations

Fast technology mapping for multiplexor-based architecture with area/delay tradeoff

Integer programming techniques for multiway system partitioning under timing and capacity constraints

Bit-alignment in hardware allocation for multiplexed DSP architectures

An assignment technique for incompletely specified data-paths

Efficient graph-based computation and manipulation of functional decision diagrams

Efficient ordered binary decision diagrams minimization based on heuristics of cover pattern processing

Input order for ROBDDs based on kernel analysis

Restructuring binary decision diagrams based on functional equivalence

An association of simulated annealing and electrical simulator SPICE-PAC for learning of analog neural networks

A novel interpolator architecture for /spl Sigma//spl Delta/ DACs

An analog spot position coding retina for active obstacle detection

A CMOS clock-frame regeneration chip with ECL-compatible input/output [for SONET]

Synthesis of weighted random sequences with application to testing of sequential circuits

On numerical weight optimization for random testing

On the design and analysis of unmatched LFSR pattern generators in pseudorandom testing

LFSROM: Basic Principle and BIST application

Restructuring of synchronous logic circuits

Sequential logic optimization based on state space decomposition

A high density datapath compiler mixing random logic with optimized blocks

A cell placement procedure that utilizes circuit structural properties

ML-Germinal: A new heuristic standard cell placement algorithm

Hierarchical test generation for VHDL behavioral models

High level testability analysis using VHDL descriptions

RT-level transformations for gate-level testability

Adding hardware for testability in synthesized data paths

Partial reset: An inexpensive design for testability approach

Automatic generation algorithms, experiments and comparisons of self-checking PLA schemes using parity codes

On self-checking design of CMOS circuits

An efficient over-the-cell channel router

Efficient OTC routing algorithm for via-less middle terminal models

Two channel routing algorithm for quickly customized logic

A parallel lookahead line search router with automatic ripup-and-reroute

VERTEX: VERification of Transistor-level circuits based on model EXtraction

Distinguishing formulas for free

Functional verification for retiming and rebuffering optimization

An automata-theoretic approach to local microcode generation

Permutation and phase independent Boolean comparison

Verifying equivalence of functions with unknown input correspondence

Methods for automatic design error correction in sequential circuits

High-level synthesis of asynchronous systems: Scheduling and process synchronization

Cooperation of synthesis, retargetable code generation and test generation in the MSS

AMICAL: An interactive high level synthesis environment

Tracking design methodology in DAMOCLES

A distributed transaction facility for design task management

A framework-based realization of an environment for formal hardware verification

Efficiency improvement for slicing point placements

An integrated algorithm for optimal floorplan sizing and enumeration

An integrated approach to pin assignment and global routing for VLSI building-block layout

Reducing the scheduling cost in event-driven simulation through component clustering

Development of parallelism for circuit simulation by tearing

Frequency domain simulation of analogue nonlinear electronic circuits

Design process beyond ASICs

1993 European Conference on Design Automation with the European Event in ASIC Design

[1992] Proceedings The European Conference on Design Automation

Proceedings of the European Conference on Design Automation.

Alleviating routing congestion by combining logic resynthesis and linear placement

Content Provider	IEEE Xplore Digital Library
Author	Shihming Liu Kuo-Rueih Pan Pedram, M. Despain, A.M.
Copyright Year	1993
Description	Author affiliation: Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA (Shihming Liu; Kuo-Rueih Pan; Pedram, M.; Despain, A.M.)
Abstract	In this approach, the logic is restructured using an intermediate placement solution and then the placement is adjusted to match the new logic structure. This ability to change logic structure during layout allows one to obtain channel density reductions that are not possible by physical design operations such as lateral shifting, pin permutation, and channel routing. Parts on an industrial chip have been resynthesized using a prototype program implementing these ideas with an average of 11.2% reduction in bit slice area compared to the original designs.<>
Starting Page	578
Ending Page	582
File Size	546716
Page Count	5
File Format	PDF
ISBN	0818634103
DOI	10.1109/EDAC.1993.386413
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-02-22
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Integrated circuit interconnections Circuit synthesis Very large scale integration Logic circuits Equations Timing Contracts Logic design Prototypes
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: ndl-support@iitkgp.ac.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in