NDLI: SAT-based sequential depth computation

Please wait, while we are loading the content...

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)

17th Asia and South Pacific Design Automation Conference

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

2009 Asia and South Pacific Design Automation Conference

2008 Asia and South Pacific Design Automation Conference

2007 Asia and South Pacific Design Automation Conference

Asia and South Pacific Conference on Design Automation, 2006.

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003.

Proceedings of the ASP-DAC 2003. Asia and South Pacific Design Automation Conference 2003 (Cat. No.03EX627)

List of reviewers

BEAM: bus encoding based on instruction-set-aware memories

Irredundant address bus encoding techniques based on adaptive codebooks for low power

Multi-parametric improvements for embedded systems using code-placement and address bus coding

Memory access pattern analysis and stream cache design for multimedia applications

A statistical gate delay model for intra-chip and inter-chip variabilities

A fast and accurate method for interconnect current calculation

Calculating the effective capacitance for the RC interconnect in VDSM technologies

Reduction of crosstalk noise by optimizing 3-D configuration of the routing grid

Design tools for 3-D integrated circuits

An on-line approach for power minimization in QoS sensitive systems

Energy minimization of real-time tasks on variable voltage processors with transition energy overhead

Register aware scheduling for distributed cache clustered architecture

Data partitioning for maximal scratchpad usage

SAT-based sequential depth computation

Logic verification based on diagnosis techniques

Algorithms for compacting error traces

Transaction-based waveform analysis for IP selection

An automatic interconnection rectification technique for SoC design integration

Typing abstractions and management in a component framework

Event-driven observability enhanced coverage analysis of C programs for functional validation

Trace-driven rapid pipeline architecture evaluation scheme for ASIP design

A hardware/software partitioning algorithm for SIMD processor cores

Approximate formulae approach for efficient inductance extraction

Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF

A metric for analyzing effective on-chip inductive coupling

Determination of worst-case crosstalk noise for non-switching victims in GHz+ interconnects

Recent developments in ESD protection for RF ICs

Temperature-independence-point properties for 0.1 /spl mu/m-scale pocket-implant technologies and the impact on circuit design

Behavioral modeling of EM devices by selective orthogonal matrix least-squares method

A BDD-based fast heuristic algorithm for disjoint decomposition

Logic optimization for asynchronous speed independent controllers using transduction method

Technology mapping for low leakage power and high speed with hot-carrier effect consideration

Synthesis of high performance low power PTL circuits

A technology mapping algorithm for heterogeneous FPGAs

Combining architecture exploration and a path to implementation to build a complete SoC design flow from system specification to RTL

Towards on-chip fault-tolerant communication

Energy-aware mapping for tile-based NoC architectures under performance constraints

Adaptive wire adjustment for bounded skew clock distribution network

Power minimization by clock root gating

BBE: hierarchical computation of 3-D interconnect capacitance with BEM block extraction

Improving boundary element methods for parasitic extraction

Statistical delay computation considering spatial correlations

Predicting short circuit power from timing models

RCLK-VJ network reduction with Hurwitz polynomial approximation

Gate-level simulation of quantum circuits

Enhanced symbolic simulation for efficient verification of embedded array systems

Hardware verification using ANSI-C programs as a reference

Evaluation of multiple-output logic functions using decision diagrams

A simulated annealing approach with sequence-pair encoding using a penalty function for the placement problem with boundary constraints

Multi-level placement for large-scale mixed-size IC designs

Selected sequence-pair: an efficient decodable packing representation in linear time using sequence-pair

An extended representation of Q-sequence for optimizing channel-adjacency and routing-cost

Non-slicing floorplans with boundary constraints using generalized Polish expression

Efficient LUT-based FPGA technology mapping for power minimization

Optimal reconfiguration sequence management [FPGA runtime reconfiguration]

On improving FPGA routability applying multi-level switch boxes

An image retrieval system using FPGAs

Logic Foundry: rapid prototyping of FPGA-based DSP systems

Leading edge low power design [SoCs]

Design methodology of low-power microprocessors

Design methodology of low-power CMOS RF-ICs

Minimizing total power by simultaneous Vdd/Vth assignment

A low power CMOS circuit with variable source scheme (VSCMOS)

Fast buffer planning and congestion optimization in interconnect-driven floorplanning

Interconnect-driven floorplanning by searching alternative packings

Noise-aware buffer planning for interconnect-driven floorplanning

Floorplanning with power supply noise avoidance

Simultaneous floorplanning and buffer block planning

A buffer planning algorithm based on dead space redistribution

VCore-based design methodology [SoC design]

Synthesis for SoC architecture using VCores

VCore-based platform for SoC design

VCDS tool demonstration [virtual core based design system]

DARPA's adaptive computing systems program

Applications of adaptive computing systems for signal processing challenges

Interactive ray tracing on reconfigurable SIMD MorphoSys

An overview of a compiler for mapping MATLAB programs onto FPGAs

Issues in debugging highly parallel FPGA-based applications derived from source code

Implementation of the super-systolic array for convolution

Design of a scalable RSA and ECC crypto-processor

A reconfigurable, power-scalable Rake receiver IP for W-CDMA

Robust high-performance low-power carry select adder

Full-custom vs. standard-cell design flow - an adder case study

A 500-MHz low-power five-port CMOS register file

An effective SDRAM power mode management scheme for performance and energy sensitive embedded systems

Branch predictor design and performance estimation for a high performance embedded microprocessor

Accelerating design space exploration using Pareto-front arithmetics [SoC design]

Quality-driven design by bitwidth optimization for video applications

Arbitrary long digit integer sorter HW/SW co-design

Legal protection for semiconductor intellectual property (IP)

Design and implementation of a video-oriented network-interface-card system

A highly efficient AES cipher chip

Implementation of fast CRC calculation

Design of a CMOS test chip for package models and I/O characteristics verification

A still image encoder based on adaptive resolution vector quantization employing needless calculation elimination architecture

Speech encoding and encryption in VLSI

The design of an i8080A instruction compatible processor with extended memory address

The design of a USB device controller IYOYOYO

MAPLE chip: a processing element for a static scheduling centric multiprocessor

Finding the best system design flow for a high-speed JPEG encoder

The design of PCI bus interface

Low-power digital CDMA receiver

Hardware implementation of an EAN-13 bar code decoder

Error correction circuit using difference-set cyclic code

Design of a digital CDMA receiver

Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 /spl mu/m technologies

A nearest-Hamming-distance search memory with fully parallel mixed digital-analog match circuitry

Run-time energy estimation in system-on-a-chip designs

SEA: fast power estimation for micro-architectures

HyPE: hybrid power estimation for IP-based programmable systems

An efficient IP-level power model for complex digital circuits

A hierarchical analysis methodology for chip-level power delivery with realizable model reduction

Optimality and scalability study of existing placement algorithms

IBM's 50 million gate ASICs

Silicon virtual prototyping: the new cockpit for nanometer chip design [SoC]

Design flow and methodology for 50M gate ASIC

Efficient loop-back testing of on-chip ADCs and DACs

A novel LCD driver testing technique using logic test channels

An implementation of memory-based on-chip analogue test signal generation

Delta-sigma modulator based mixed-signal BIST architecture for SoC

Capturing and analyzing requirement - in case of software and applying to hardware

A comparison of the RTU hardware RTOS with a hardware/software RTOS

Linux kernel customization for embedded systems by using call graph approach

Topology selection for energy minimization in embedded networks

Semi-formal test generation and resolving a temporal abstraction problem in practice: industrial application

Scan-chain based watch-points for efficient run-time debugging and verification of FPGA designs

A novel approach for digital waveform compression [IC simulation data]

A deep submicron power estimation methodology adaptable to variations between power characterization and estimation

Congestion driven incremental placement algorithm for standard cell layout

Performance-driven multi-level clustering for combinational circuits

Cross talk driven placement

VLSI module placement with pre-placed modules and considering congestion using solution space smoothing

A path-based timing-driven quadratic placement algorithm

Experience in critical path selection for deep sub-micron delay test and timing validation

On effective criterion of path selection for delay testing

DFT timing design methodology for at-speed BIST

An automated method for test model generation from switch level circuits

Using red-black interval trees in device-level analog placement with symmetry constraints

Current-driven wire planning for electromigration avoidance in analog circuits

Efficient DDD-based term generation algorithm for analog circuit behavioral modeling

5 Gbps serial link transmitter with pre-emphasis

Low power synthesis of finite state machines with mixed D and T flip-flops

Don't cares in logic minimization of extended finite state machines

Performance optimization of synchronous control units for datapaths with variable delay arithmetic units

Integer linear programming-based synthesis of skewed logic circuits

Highly scalable algorithms for rectilinear and octilinear Steiner trees

UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing

The Y-architecture: yet another on-chip interconnect solution

A novel timing-driven global routing algorithm considering coupling effects for high performance circuit design

Graph matching-based algorithms for array-based FPGA segmentation design and routing

Routing-aware scan chain ordering

Multiple test set generation method for LFSR-based BIST

A seed selection procedure for LFSR-based random pattern generators

Efficient BIST design for sequential machines using FiF-FoF values in machine states

A new design-for-test technique for reducing SOC test time

Periodic steady-state analysis of coupled ODE-AE-CGE systems for MOS RF autonomous circuit simulation

A frequency separation macromodel for system-level simulation of RF circuits

Nonlinear distortion analysis via linear-centric models

Parasitic-aware design and optimization of a fully integrated CMOS wideband amplifier

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)

Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106)

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)

Proceedings of 1998 Asia and South Pacific Design Automation Conference

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair

SAT-based sequential depth computation

Content Provider	IEEE Xplore Digital Library
Author	Mneimneh, M. Sakallah, K.
Copyright Year	2003
Description	Author affiliation: Michigan Univ., MI, USA (Mneimneh, M.; Sakallah, K.)
Abstract	Determining the depth of sequential circuits is a crucial step towards the completeness of bounded model checking proofs in hardware verification. In this paper, we formulate sequential depth computation as a logical inference problem for quantified Boolean formulas. We introduce a novel technique to simplify the complexity of the constructed formulas by applying simple transformations to the circuit netlist. We also study the structure of the resulting simplified QBFs and construct an efficient SAT-based algorithm to check their satisfiability. We report promising experimental results on some of the ISCAS 89 benchmarks.
Sponsorship	IEEE Circuits & Syst. Soc. ACM SIGDA IEICE (Inst. Electon., Inf. & Commun. Eng.) IPSJ (Inf. Process. Soc. Japan)
Starting Page	87
Ending Page	92
File Size	671437
Page Count	6
File Format	PDF
ISBN	0780376595
DOI	10.1109/ASPDAC.2003.1194998
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-01-24
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Data structures Boolean functions Hardware Binary decision diagrams Sequential circuits Inference algorithms Product design Circuit faults Time to market Costs
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: ndl-support@iitkgp.ac.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in