NDLI: WearMon: Reliability monitoring using adaptive critical path testing

Content Provider	IEEE Xplore Digital Library
Author	Zandian, B. Dweik, W. Suk Hun Kang Punihaole, T. Annavaram, M.
Copyright Year	2010
Description	Author affiliation: Electrical Engineering Department, University of Southern California, USA (Zandian, B.; Dweik, W.; Suk Hun Kang; Punihaole, T.; Annavaram, M.)
Abstract	As processor reliability becomes a first order design constraint, this research argues for a need to provide continuous reliability monitoring. We present WearMon, an adaptive critical path monitoring architecture which provides accurate and real-time measure of the processor's timing margin degradation. Special test patterns check a set of critical paths in the circuit-under-test. By activating the actual devices and signal paths used in normal operation of the chip, each test will capture up-to-date timing margin of these paths. The monitoring architecture dynamically adapts testing interval and complexity based on analysis of prior test results, which increases efficiency and accuracy of monitoring. Experimental results based on FPGA implementation show that the proposed monitoring unit can be easily integrated into existing designs. Monitoring overhead can be reduced to zero by scheduling tests only when a unit is idle.
Starting Page	151
Ending Page	160
File Size	1466759
Page Count	10
File Format	PDF
ISBN	9781424475001
e-ISBN	9781424475018
e-ISBN	9781424474998
DOI	10.1109/DSN.2010.5544916
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing Circuit testing Semiconductor device measurement Electric breakdown Niobium compounds Titanium compounds Thermal degradation Condition monitoring System testing Field programmable gate arrays Timing Margins Reliability Critical Paths
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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