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2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - itle Page

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Copyright

Message from the Symposium Chairs

Defects, yield, and design in sublithographic nano-electronics

An ILP formulation for yield-driven architectural synthesis

Design and analysis of self-repairable MEMS accelerometer

Low power BIST based on scan partitioning

Using statistical transformations to improve compression for linear decompressors

Securing Scan Design Using Lock and Key Technique

A genetic approach for the reconfiguration of degradable processor arrays

Incorporating error detection and online reconfiguration into a regular architecture for the advanced encryption standard

An integrated ECC and redundancy repair scheme for memory reliability enhancement

Error control coding for semiconductor memory systems in the space radiation environment

Concurrent error detection of polynomial basis multiplication over extension fields using a multiple-bit parity scheme

A self checking Reed Solomon encoder: design and analysis

Transient behavior of the encoding/decoding circuits of error correcting codes

Flash memory cell: parametric test data reconstruction for process monitoring

Noise analysis of fault tolerant active pixel sensors

On-line identification of faults in fault-tolerant imagers

Inter-plane via defect detection using the sensor plane in 3D heterogeneous sensor systems

The other side of the timing equation: a result of clock faults

A fast algorithm for critical path tracing in VLSI digital circuits

Improving transition delay fault coverage using hybrid scan-based technique

Defect characterization and tolerance of QCA sequential devices and circuits

Modeling QCA defects at molecular-level in combinational circuits

QCA-based majority gate design under radius of effect-induced faults

A novel pulse echo correlation tool for transmission path testing and fault finding using pseudorandom binary sequences

Methodologies and algorithms for testing switch-based NoC interconnects

Test of interconnection opens considering coupling signals

FPGA oriented design of parity sharing RS codecs

A software-based concurrent error detection technique for power PC processor-based embedded systems

Soft errors induced by single heavy ions in floating gate memory arrays

On the modeling and analysis of jitter in ATE using Matlab

Data dependent jitter (DDJ) characterization methodology

Defect tolerance for molecular electronics-based nanofabrics using built-in self-test procedure

Reliable digital circuits design using sigma-delta modulated signals

A technique for modular design of self-checking carry-select adder

A model of soft error effects in generic IP processors

Implementation of concurrent checking circuits by independent sub-circuits

Multiple transient faults in logic: an issue for next generation ICs?

Efficient exact spare allocation via Boolean satisfiability

On the effect of stuck-at faults on delay-insensitive nanoscale circuits

Delay test generation with all reachable output propagation and multiple excitations

Simulating faults of combinational IP core-based SOCs in a PLI environment

On generating pseudo-functional delay fault tests for scan designs

Should Illinois-scan based architectures be centralized or distributed?

On generating tests to cover diverse worst-case timing corners

Computing cache vulnerability to transient errors and its implication

A design flow for protecting FPGA-based systems against single event upsets

An integrated approach for increasing the soft-error detection capabilities in SoCs processors

A low power soft error suppression technique for dynamic logic

Soft error modeling and protection for sequential elements

Recovery during concurrent on-line testing of identical circuits

Efficient failure detection in pipelined asynchronous circuits

On the transformation of manufacturing test sets into on-line test sets for microprocessors

Fault-tolerant wormhole switching with backtracking capability

Analysis and testing for error tolerant motion estimation

Hardware testing for error tolerant multimedia compression based on linear transforms

Software-based self-test for pipelined processors: a case study

Improving thermal-safe test scheduling for core-based systems-on-chip using shift frequency scaling

Thermal-aware test scheduling and hot spot temperature minimization for core-based systems

Design of a CMOS operational amplifier amenable to extreme voltage stress

Characteristics of fault diagnosis for analog circuits based on preset test

A new test methodology for DNL error in flash ADCs

A high frequency, low jitter auto-calibration phase-locked loop with built-in-self-test

19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings.

Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems

17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings.

Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)

Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)

1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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