NDLI: BRAINS: a BIST compiler for embedded memories

Content Provider	IEEE Xplore Digital Library
Author	Chuang Cheng Chih-Tsun Huang Jing-Reng Huang Cheng-Wen Wu Chen-Jong Wey Ming-Chang Tsai
Copyright Year	2000
Description	Author affiliation: Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan (Chuang Cheng)
Abstract	A built-in self-test (BIST) compiler for embedded memories, called BRAINS (Bist for RAm IN Seconds), is proposed. According to the memory specifications and test requirements entered by the user, BRAINS generates the synthesizable BIST code in Verilog as well as the corresponding BIST activation sequence and test-bench. The synthesis scripts for a commercial synthesis tool are also generated automatically. The architecture for the BIST circuits generated by BRAINS is an improved version of our previous design. The new design provides at-speed testing, diagnosis support, and programmable March test algorithms. The BIST compiler framework facilitates the generation of BIST circuits for various SRAM and DRAM architectures and configurations-BRAINS supports commonly used memory cores such as SRAM, EDO DRAM, SDRAM, etc. It is easy to use BRAINS for customized embedded memories. We have designed the system so that future extension to other types of memory can be done under the same framework.
Starting Page	299
Ending Page	307
File Size	629506
Page Count	9
File Format	PDF
ISBN	0769507190
ISSN	10636722
DOI	10.1109/DFTVS.2000.887170
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-10-27
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test Random access memory Circuit synthesis Circuit testing Circuit faults Algorithm design and analysis Costs Automatic testing SDRAM System-on-a-chip
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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