NDLI: Crosstalk minimization in three-layer HVH channel routing

Please wait, while we are loading the content...

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)

19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings.

Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems

17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings.

Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)

Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)

1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Improved yield model for submicron domain

Application of a yield model merging critical areas and defectivity to industrial products

Efficient critical area estimation for arbitrary defect shapes

Realistic fault extraction for high-quality design and test of VLSI systems

Crosstalk minimization in three-layer HVH channel routing

Analysis of defect to yield correlation on memories: method, algorithms and limits

An examination of empirically derived within-die local probabilities of failure

Detection of yield trends

A statistical approach to identify semiconductor process equipment related yield problems

Testing of programmable logic devices (PLD) with faulty resources

Configuration-specific test pattern extraction for field programmable gate arrays

Concurrent testing of VLSI digital signal processors using mutation based testing

Generation and verification of tests for analogue circuits subject to process parameter deviations

Fast and area-time efficient Berger code checkers

Design of encoders and self-testing checkers for some systematic unidirectional error detecting codes

Design of compact and high speed totally self-checking CMOS checkers for m-out-of-n codes

Compact and low power on-line self-testing voting scheme

A cost model for VLSI/MCM systems

Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model

Analysis of a hybrid defect-tolerance scheme for high-density memory ICs

Validating fault tolerant designs using laser fault injection (LFI)

Multiple fault detection in logic resources of FPGAs

Automatic and optimized synthesis of dataparts with fault detection or tolerance capabilities

Designing ad-hoc codes for the realization of fault tolerant CMOS networks

Exploiting high-level descriptions for circuits fault tolerance assessments

Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits

Fault-tolerant hierarchical interconnection networks constructed by additional bypass linking with graph-node coloring

Low-level error recovery mechanism for self-checking sequential circuits

Fast error-correcting Newton-Raphson dividers using time shared TMR

Error identification and data recovery in MISR-based data compaction

Harvesting through array partitioning: a solution to achieve defect tolerance

An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring

An IDDQ sensor for concurrent timing error detection

Designing networks with error detection properties through the fault-error relation

Semi-concurrent error detection in data paths

On-line error detection for finite field multipliers

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Crosstalk minimization in three-layer HVH channel routing

Content Provider	IEEE Xplore Digital Library
Author	Zhan Chen Koren, I.
Copyright Year	1997
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA (Zhan Chen)
Abstract	Crosstalk has become a major issue in VLSI design due to the high frequency, long interconnecting lines and small spacing between interconnects in today's integrated circuits. In this paper, we study the problem of crosstalk minimization in 3-layer HVH channel routing. A heuristic algorithm that combines layer reassignment and track reassignment is presented. This algorithm can iteratively modify the layout so that the crosstalk in the channel is minimized. Experimental results show that the proposed approach can reduce the crosstalk by an average of 16.4% on a set of benchmark examples.
Starting Page	38
Ending Page	42
File Size	316829
Page Count	5
File Format	PDF
ISBN	0818681683
ISSN	10636722
DOI	10.1109/DFTVS.1997.628307
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-10-20
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Crosstalk Routing Wire Minimization Very large scale integration Integrated circuit interconnections Integrated circuit noise Iterative algorithms Frequency Heuristic algorithms
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: ndl-support@iitkgp.ac.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in