NDLI: Analysis of the floating gate defect in CMOS

Content Provider	IEEE Xplore Digital Library
Author	Champac, V.H. Rubio, A. Figueras, J.
Copyright Year	1993
Description	Author affiliation: Dept. d'Enginyeria Electron., Univ. Politecnica de Catalunya, Barcelona, Spain (Champac, V.H.)
Abstract	The floating gate transistor is modeled using the coupling capacitances in the floating gate and the charge in the transistor gate. The location of the open in the open track influences the value of the poly-bulk and metal-poly capacitances who determines the degree of conduction of the defective transistor. The induced voltage in the floating gate and the quiescent current are estimated by means of analytical expressions. A good agreement is observed between the simple analytical expressions, simulations (SPICE) and experimental measures performed on defective circuits. It is shown that a floating gate transistor is not a stuck-open transistor and that significative values of quiescent current consumption may exist.
Starting Page	101
Ending Page	108
File Size	418203
Page Count	8
File Format	PDF
ISBN	0818635029
ISSN	10636722
DOI	10.1109/DFTVS.1993.595713
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-10-27
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage Capacitance Analytical models Circuit topology Coupling circuits SPICE Circuit testing Semiconductor device modeling Performance analysis Performance evaluation
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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