NDLI: A band-reject nested-PLL phase-noise reduction scheme for clock-cleaners

Content Provider	IEEE Xplore Digital Library
Author	Pardo, M. Ayazi, F.
Copyright Year	2011
Description	Author affiliation: Georgia Institute of Technology, Atlanta, USA (Pardo, M.; Ayazi, F.)
Abstract	This paper proposes a clock-conditioner architecture that minimizes the incidence of the input signal phase-noise (PN) in phase-locked-loop (PLL)-based cleaners by modifying the corresponding transfer function from band-pass to band-reject. Although the proposed configuration uses two PLLs, just one cut-off frequency exists eliminating the need for ultra narrow-band loops. Relaxed bandwidth requirements translate to smaller capacitor values in the loop filters which considerably reduce the overall footprint of the architecture. A 100 MHz clock-cleaner is demonstrated using ICs fabricated in a 0.5 µm 2P3M CMOS process. Experimental results show a 20dB PN improvement at 1 kHz offset frequency with only 3.5% of the capacitor area used in a state-of-the-art cascade-type PLL clock-cleaner.
Starting Page	470
Ending Page	473
File Size	516566
Page Count	4
File Format	PDF
ISBN	9781424494736
ISSN	02714302
e-ISBN	9781424494743
e-ISBN	9781424494729
DOI	10.1109/ISCAS.2011.5937604
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-05-15
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase locked loops Clocks Noise Transfer functions Bandwidth Capacitors Band pass filters
Content Type	Text
Resource Type	Article

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