NDLI: Self-timed simultaneous bidirectional signalling for IC systems

Content Provider	IEEE Xplore Digital Library
Author	Yacoub, G.Y. Ku, W.H.
Copyright Year	1992
Description	Author affiliation: California Univ., San Diego, CA, USA (Yacoub, G.Y.; Ku, W.H.)
Abstract	The authors present a self-timed architectural interface design for VLSI CMOS integrated circuit systems. The interface follows a two-cycle self-timed bundled data protocol and nearly doubles the input/output (I/O) bandwidth for wide bus VLSI interprocessor communication by simultaneously sending and receiving data over the same wires. A constant overhead of four control wires is incurred over the synchronous approach proposed by K. Lam et al. (1990), as well as a decaying area penalty for increasing bus widths. This type of self-timed bundled interface can prove attractive for applications where global synchronization is difficult to achieve. The interface has been simulated for a 16-b wide bus using a quasi-analog mixed-signal Verilog approach.<>
Starting Page	2957
Ending Page	2960
File Size	289819
Page Count	4
File Format	PDF
ISBN	0780305930
DOI	10.1109/ISCAS.1992.230701
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-05-10
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pulse amplifiers Very large scale integration Protocols Wires Transmitters Impedance Clocks Postal services CMOS integrated circuits Bandwidth
Content Type	Text
Resource Type	Article

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Self-timed simultaneous bidirectional signalling for IC systems