NDLI: A reconfigurable 'ANN' architecture

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A new time-evolving neural network architecture and algorithm for nonlinear system identification using adaptive filtering techniques

A neutral binary multiplier and divider

Detection and estimation of chirp signals using state space representation

Designing prototype filters for perfect-reconstruction cosine-modulated filter banks

Design methodology of 16-bit Sigma-Delta A/D and D/A converters in a single chip

Transform domain LMS adaptation of split-path filter

Blind adaptive channel equalization using the unsupervised cluster formation technique

A state-variable approach to symbolic circuit simulation in the time domain

A hybrid NeoART/EBP architecture for hand-written digit recognition

A perceptron-based adaptive equalizer for PAM signals

SANNET: Image compression and regeneration by nonlinear associative silicon retina

Synthesis and implementation of T-model neural-based A/D converter

A reconfigurable 'ANN' architecture

Circuit implementation of trainable neural networks employing both supervised and unsupervised techniques

A refreshable multilevel memory for a continuous-time synapse

Ring unidirectional associative memories

Classification-accuracy monitored backpropagation

Distributed key-generation structures for associative image-classification

Required dynamic range and accuracy of electronic synapses for character recognition applications

A hybrid architecture for feed-forward multi-layer neural networks

Switched-current techniques for image processing cellular neural networks in MOS VLSI

Modular analog continuous-time VLSI neural networks with on-chip Hebbian learning and analog storage

Architectures for analog VLSI implementation of neural networks for solving linear equations with inequality constraints

Architectures and building blocks for CMOS VLSI analog 'neural' programmable optimizers

Filterless amplitude detection of multiphase sinusoidal waveforms

Interconnection network switch design for parallel DSP systems

Multiparametric multiscale filtering, multiparametric granulometries and the associated pattern spectra

Ring structure and multi-dimensional discrete Fourier transform on a power of 2

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A numerical approach to the synthesis of recursive phase equalizers

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User-interactive knowledge-based speech enhancement

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Cross coupled signal controlled constrained null filter and separation of superimposed frequency modulated sinusoids

Direct recovering of Nth order surface structure using UOFF approach

Time-varying analysis using ARMA model with double inputs

Gradient techniques for voiced/unvoiced speech signal representation using mixed transforms

Bearing (frequency) estimation via MUSIC spectrum estimator without eigendecomposition

Wigner distribution analysis of linear, time-varying systems

Time frequency weighting and displacement effects in linear, time-varying systems

Probabilistic rejectionless anti-voter optimization algorithm

2-D sliding spectrum analysis

Finite memory realization of 2D FIR filters

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2-D state-space filter structures with low frequency-weighting sensitivity

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A quadratic-constrained least-squares approach to the design of digital filter banks

Finite wordlength effects in quadrature mirror filter banks

Comparison of filterbanks for high quality audio coding

A class of DFT polyphase filter banks for orthogonal multiple carrier data transmission

A method for the evaluation of multirate sigma-delta systems

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Switched-current sigma-delta modulation for A/D conversion

Stability tests for single-bit sigma-delta modulators with second-order FIR noise transfer functions

Stability and scaling of double loop Sigma Delta modulators

Multiplexed noise shaping structures for delta-sigma modulators

Effective dithering of sigma-delta modulators

Components for a GaAs delta-sigma modulator oversampled analog-to-digital converter

Sigma Delta modulation from the perspective of nonlinear dynamics

New CMOS current Schmitt triggers

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Nonlinearities of capacitors realized by MOSFET gates

Accurate MOS threshold voltage detector for bias circuitry

CMOS absolute value precision capacitance measurement system

Bi-CMOS current mode circuits with 1 V supply voltage and their application to ADC

An adjustable threshold MOSFET

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Applications of BiCMOS composite transistors in analog circuits

A study of the use of local interconnect in CMOS leaf cell design

Design-for-reliability rules for hot-carrier resistant CMOS VLSI circuits

A LMS algorithm with stochastic momentum factor

Parallel recursive least squares algorithms for adaptive Volterra filters

Ratioed voter circuit for testing and fault-tolerance in VLSI processing arrays

Redundancy identification and removal in combinational logic circuits

Acceleration of fault propagation trace-based fault simulation of combinational circuits

New results and algorithms for MCM substrate testing

Fault detection in EEPLA

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Area and latency efficient CORDIC architectures

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Highly modular and concurrent 2-D DCT chip

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Median filter architecture based on sorting networks

VLSI architectures for a high-speed tunable digital modulator/ demodulator/bandpass-filter chip set

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IIR adaptive filters using discrete orthogonal functions

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Two-dimensional block adaptive filtering algorithms

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Linearity of switched capacitor filters employing nonlinear capacitors

Biquadratic transconductance switched capacitor filters

Optimum pairing and ordering conditions for simultaneous reduction in total capacitance, sensitivity and output noise of cascade SC filters

High frequency switched capacitor IIR filters using parallel cyclic type circuits

Clock-feedthrough compensated switched-capacitor circuits

A switched-capacitor inductance simulation circuit realized with current conveyors

Area-efficient gain- and offset-compensated very-large-time-constant SC biquads

Multi-rate switched capacitor filter design with aggressive sampling-rates: filtorX in action

An improved double sampling scheme for switched-capacitor delta-sigma modulators

SAUCES: a sensitivity analysis program for analog circuit design

A user-friendly implementation of PC-SNAP

Network symbolic analysis for automated fault diagnosis

Applications of symbolic analysis to analog system design

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Improved test pattern generation for sequential circuits using implicit enumeration

Delay-fault diagnosis based on critical path tracing from symbolic simulation

Testable design of bit-level systolic block FIR filters

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A reconfigurable 'ANN' architecture

Content Provider	IEEE Xplore Digital Library
Author	Madraswala, T.H. Mohd, B.J. Ali, M. Premi, R. Bayoumi, M.A.
Copyright Year	1992
Description	Author affiliation: Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA (Madraswala, T.H.; Mohd, B.J.; Ali, M.; Premi, R.; Bayoumi, M.A.)
Abstract	Proposes a design of a digital artificial neural network (ANN). The architecture is based on a single-instruction multiple-data (SIMD) processing configuration. Communication is done through broadcasting and also by systolic methods. With the help of a microprogrammed control unit, the design is mainly capable of implementing the following three models: (1) Hamming, (2) Hopfield, and (3) Carpenter/Grossberg algorithms. The architecture was also designed to achieve parallelism, modularity, adaptability, flexibility, speed, low cost, smaller silicon area, and expandability.<>
Starting Page	1569
Ending Page	1572
File Size	304950
Page Count	4
File Format	PDF
ISBN	0780305930
DOI	10.1109/ISCAS.1992.230198
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-05-10
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Neural networks Costs Artificial neural networks Computer architecture Integrated circuit interconnections Silicon Neurons Computer networks Very large scale integration Machine learning
Content Type	Text
Resource Type	Article

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