NDLI: A high-efficiency CMOS charge pump circuit

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2015 IEEE International Symposium on Circuits and Systems (ISCAS)

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

2012 IEEE International Conference on Circuits and Systems (ICCAS)

2012 IEEE International Symposium on Circuits and Systems

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

2009 IEEE International Symposium on Circuits and Systems

2008 IEEE International Symposium on Circuits and Systems

2007 IEEE International Symposium on Circuits and Systems

2006 IEEE International Symposium on Circuits and Systems

2005 IEEE International Symposium on Circuits and Systems

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.

The IEEE International Symposium on Circuits and Systems, 2003. Tutorial Guide: ISCAS 2003.

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)

Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)

Volume 5 - 2001

Volume 4 - 2001

The 2001 IEEE International Symposium on Circuits and Systems

Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT

Testing complementary pass-transistor logic circuits

At-speed testing of data communications transceivers

Built-In self-repair for divided word line memory

FDP: fault detection probability function for analog circuits

Statistical analysis of the time-delay digital tanlock loop in the presence of Gaussian noise

An all-lag rotating-reference correlator and its efficient implementation

Noise generation system using DCT

Systolic VLSI realization of a novel iterative division algorithm over GF(2/sup m/): a high-speed, low-complexity design

A low-power bit-serial multiplier for finite fields GF(2/sup m/)

A low power MMSE receiver architecture for multi-carrier CDMA

PN-generators embedded in high performance signal processors

Nonuniform amplitude division for ABLMS equalisation

Robust chaotic PN sequence generation techniques

VLSI architecture design and implementation for BLOWFISH block cipher with secure modes of operation

A 2.5 Mb/s, 23 mW SOVA traceback chip for turbo decoding applications

A study on the performance, complexity tradeoffs of block turbo decoder design

3V CMOS 0.35 u transimpedance receiver for optical applications

A serial link transceiver for USB2 high-speed mode

Pipelined implementation of the adaptive canceller-equalizer

A 1.25 GHz 32-bit tree-structured carry lookahead adder

A 2.8 ns 30 /spl mu/W/MHz area-efficient 32-b Manchester carry-bypass adder

A high-speed CMOS incrementer/decrementer

Scalable counter architecture for a pre-loadable 1 GHz@0.6 /spl mu/m/5V pre-scaler in TSPC

A compact layout technique to minimize high frequency switching effects in high speed circuits

A low-power fully integrated Gaussian-MSK modulator based on the sigma-delta fractional-N frequency synthesis

A new design for cascaded sigma-delta modulators

A low power sinusoidal clock

CML ring oscillators: oscillation frequency

An 8-Bit, 100-MHz low glitch interpolation DAC

A comparative analysis of direct-sequence spread-spectrum super-regenerative architectures

Image-reject receivers with image-selection functionality

A bit-streaming, pipelined multiuser detector for wireless communication receivers

A novel single-bit input all digital synchronizer and demodulator baseband processor for fast frequency hopping system

A design of source matched MAP receiver for image transmission

A CMOS differential logic for low-power and high-speed applications

Dynamic single phase logic with self-timed stages for power reduction in pipeline circuit designs

A low-power 3-phase half rail pass-gate differential logic

CRRDL: a novel charge recovery-recycling differential logic

Skew-tolerant high-speed (STHS) domino logic

Noise constrained power optimization for dual V/sub T/ domino logic

The circuit design of multiple-valued logic voltage-mode adders

A regular parallel multiplier which utilizes multiple carry-propagate adders

Asynchronous interface for locally clocked modules in ULSI systems

Strategies for on-chip sub-nanosecond signal capture and timing measurements

Leakage power estimation and minimization in VLSI circuits

A new logic synthesis and optimization procedure

Minimizing gate capacitances with transistor sizing

A low-cost CMOS time interval measurement core

Modified SRCMOS cell for high-throughput wave-pipelined arithmetic units

On mismatch errors in analog-VLSI error correcting decoders

On finite precision implementation of low density parity check codes decoder

VLSI architecture of extended in-place path metric update for Viterbi decoders

A novel ACS-feedback scheme for generic, sequential Viterbi-decoder macros

A low power survivor memory unit for sequential Viterbi-Decoders

A low power carry select adder with reduced area

Using carry-save adders in low-power multiplier blocks

A low power 10-transistor full adder cell for embedded architectures

An embedded low power FIR filter

Low power enhancements for parallel algorithms

A multi-gigabit CMOS data recovery circuit using an analog parallel sampling technique

System-on-chip design of a four-port ADSL-lite Data DSP

On-chip automatic direct tuning circuitry based on the synchronous rectification scheme for CMOS gigahertz band front-end filters

An improved time-recursive lattice structure for low-latency IFFT architecture in DMT transmitter

An efficient model for twisted-pair cables with discontinuities and stubs for discrete time simulations

A system level description and model of Signaling System No. 7

A mesh based motion tracking architecture

A CMOS clock and data recovery with two-XOR phase-frequency detector circuit

A reflectance-based computer aided modelling tool for high speed/high frequency communication systems

Shared memory switching + virtual output queuing: A robust and scalable switch

VLSI considerations in the design of k-ary n-cube interconnection networks

Phase tracking of CDMA spreading sequences using dynamic chaotic synchronization

Adaptive interference suppression with power control for CDMA systems

Numerical word-length optimization for CDMA demodulator

New AFC algorithm for a fully-digital MDPSK DS/CDMA receiver

A near-optimal multiuser detector for CDMA channels using semidefinite programming relaxation

Customizable DSP architecture for ASIP core design

Register-based multi-port perfect shuffle networks

Self-reorganising systems on VLSI circuits

A reconfigurable pipelined data converter

Novel radix-2/sup k/ division algorithm

A parallel architecture for estimating 4th-order cumulants

Error resilient hybrid variable length codec with tough error synchronization for wireless image transmission

A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme

On the implementation of a baseband processor for a portable dual mode DECT/GSM terminal

A low-complexity and high-speed Booth-algorithm FIR architecture

A VLSI architecture of a piecewise RBF decision feedback channel equalizer

Cellular-array power-sum circuits over programmable finite field GF(2''')

FPGA realization of RNS to binary signed conversion architecture

Design and implementation of channel equalizers for block transmission systems

A wide pull-in range fast acquisition hardware-sharing two-fold carrier recovery loop

FIR prefilter design for MLSE equalization of space-time-coded transmission over multipath fading channels

Second order statistics based blind channel equalization with correlated sources

Adaptive compensation of analog front-end I/Q mismatches in digital receivers

A single-chip CMOS front-end receiver architecture for multi-standard wireless applications

A 2.4 GHz four port mixer for direct conversion used in telemetering

Design of low-voltage active mixer for direct conversion receivers

A CMOS self-mixing-free front-end for direct conversion applications

A low power monolithic AGC with automatic DC offset cancellation for direct conversion hybrid CDMA transceiver used in telemetering

Dynamically biased current sensor for current-sensing completion detection

Process variation independent built-in current sensor for analogue built-in self-test

Modeling and minimization of power consumption in charge pump circuits

A high-efficiency CMOS charge pump circuit

Active threshold compensation circuit for improved performance in cooled CMOS systems

Power trends and performance characterization of 3-dimensional integration

Low-voltage swing clock distribution schemes

A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty

Minimizing process-induced skew using delay tuning

Non-linearity reduction technique for delay-locked delay-lines

Closed-form design of tunable fractional-delay allpass filter structures

A low complexity adaptive interpolated FIR echo canceller

An enhancement study on the SDSL upstream receiver

A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter

An adaptive mixed-signal narrowband interference canceller for wireline transmission systems

A 1-V 2.4-GHz CMOS RF receiver front-end for Bluetooth application

A linear-control wide-band CMOS attenuator

Fully integrated low-noise-amplifier with high quality factor L-C filter for 1.8 GHz wireless applications

A 2 V 2.4 GHz fully integrated CMOS LNA

Dual-loop cross-coupled feedback amplifier for low-IF integrated receiver architecture

Enhanced low power motion estimation VLSI architectures for video compression

Interfacing multiple processors in a system-on-chip video encoder

A vector processor for 3-D geometrical transformations

A system-on-chip realization of a CMOS image sensor with programmable analog image preprocessing

An analogue SIMD focal-plane processor array

Low power techniques for flash memories

Development of a low-power SRAM compiler

Fast system-level exploration of memory architectures driven by energy-delay metrics

Static power consumption management in CMOS memories

A low power charge-recycling ROM architecture

Public-domain Matlab program to generate highly optimized VHDL for FPGA implementation

Hardware implementation of the depth first search bit stream SPIHT system

A low complexity FEC design for DAB

A microprocessor based system for ECG telemedicine and telecare

SIMD architecture for job shop scheduling problem solving

A hardware design approach for merge-sorting network

A low power asynchronous DES

Reconfigurable and programmable minimum distance search engine for portable video compression systems

A flexible multiplication unit for an FPGA logic block

A retiming-based test pattern generator design for built-in self test of data path architectures

Hybrid wavelet/spread-spectrum system for broadband wireless LANs

Design of an OFDM receiver for high-speed wireless LAN

Peak-to-average power ratio reduction of an OFDM signal using data permutation with embedded side information

Forward error correction codes to reduce intercarrier interference in OFDM

Blind frequency offset estimation for PCC-OFDM with symbols overlapped in the time domain

Custom VLSI design of efficient low latency and low power finite field multiplier for Reed-Solomon codec

New bit-parallel systolic multipliers for a class of GF(2/sup m/)

A low-power variable length decoder based on successive decoding of shoft codewords

Bit-level pipelined digit serial GF(2/sup m/) multiplier

Multi-level low swing voltage values for low power design applications

Effectivity of standby-energy reduction techniques for deep sub-micron CMOS

A power-on reset pulse generator for low voltage applications

Control loop for optimization of power consumption in VLSI designs

A low power and area efficient FIR filter chip for PRML read channels

A giga-hertz CMOS digital controlled oscillator

A low-power high driving ability voltage control oscillator used in PLL

High-speed serial communication with error correction using 0.25 /spl mu/m CMOS technology

New structures for very high-frequency CMOS clock dividers

A 30 MHz DDS clock generator with sub-ns time domain interpolator and -50 dBc spurious level

Oscillatorless clock multiplication

High-speed CMOS logic circuits in capacitor coupling technique

An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores

Efficient power clock generation for adiabatic logic

Fast and low-power inner product processor

Two implementation methods of a 1024-bit RSA cryptoprocessor based on modified Montgomery algorithm

Design of an efficient FFT processor for DAB system

A low cost 2-D inverse discrete cosine transform design for image compression

A new DA-based array for one dimensional discrete Hartley transform

Low-power multiplierless FIR filter synthesizer based on CSD code

A new memory-based FFT processor for VDSL transceivers

A VLSI implementation of a universal programmable low sensitivity sampled data filter

Circuit realization of spectral transforms in Fibonacci interconnection topologies

Reed-Muller descriptions of symmetric functions

Dynamic range boosting for wireless optical receivers

110 MHz IF-baseband CMOS receiver for J-CDMA/AMPS application

An ISM band CMOS integrated transceiver design for wireless telemetry system

A 3.3-V analog front-end chip for HomePNA applications

Design and implementation of CMOS LVDS 2.5 Gb/s transmitter and 1.3 Gb/s receiver for optical interconnections

A CMOS triple-band fractional-N frequency synthesizer for GSM/GPRS/EDGE applications

A wideband digital frequency synthesizer

A 1.8-GHz monolithic CMOS VCO tuned by an inductive varactor

Power optimization of CMOS LC VCOs

A CMOS PLL-based frequency synthesizer for wireless communication systems at 0.9, 1.8, 1.9 and 2.4 GHz

Implementation of encryption algorithms on transport triggered architectures

A CAD tool for architecture level exploration and automatic generation of RNS converters

VLSI architecture of dynamically reconfigurable hardware-based cipher

A bit-serial column parallel processing architecture for on-sensor discrete Fourier transform

Parallel decoding architectures for low density parity check codes

Design-for-ESD-reliability for high-frequency I/O interface circuits in deep-submicron CMOS technology

Evaluation of substrate noise in CMOS and low-noise logic cells

ESD protection design in a 0.18-/spl mu/m salicide CMOS technology by using substrate-triggered technique

Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes

Highly linear TX IF-chip for multicarrier GSM 900 and 1800 base station

Sample-reset loop filter architecture for process independent and ripple-pole-less low jitter CMOS charge-pump PLLs

Design and optimization of CMOS switches for switched tuning of LC resonators

Analysis and experimental characterization of idle tones in 2nd-order bandpass /spl Sigma//spl Delta/ modulators-a 0.8 /spl mu/m CMOS switched-current case study

MASH delta-sigma modulators for wideband and multi-standard applications

A 1.5 V high gain CMOS mixer for 2.4-GHz applications

Analysis and design of an integrated quadrature mixer with improved noise, gain and image rejection

A low noise quadrature subsampling mixer

A 2.4-GHz CMOS down-conversion doubly balanced mixer with low supply voltage

Split-Gate Logic circuits for multi-threshold technologies

A high-performance low-power static differential double edge-triggered flip-flop

A low-power reduced swing single clock flip-flop

A new controlled gain phase-locked loop technique

A new PLL design for clock management applications

New method of on-sensor A/D conversion

Modeling of a floating-gate EEPROM cell using a charge sheet approach including variable tunneling capacitance and polysilicon gate depletion effect

A digital Class D amplifier design embodying a novel sampling process and pulse generator

Development of a dynamic routing system for a fault tolerant solid state mass memory

A 2.3 V low noise, low power, 10 GHz bandwidth Si-bipolar transimpedance preamplifier for optical receiver front-ends

Exploiting sinh and tanh shaped ultra low-voltage floating-gate transconductance amplifiers to reduce harmonic distortion

A fully integrated 1 V 5.8 GHz bipolar LNA

EEPROM programming study-time and degradation aspects

VLSI design and implementation of analog CMOS 2/sup nd/ generation current conveyors

Fault isolation in nonlinear analog circuits with tolerance using the neural network-based L/sub 1/-norm

Emerging adaptive antenna techniques for wireless ad-hoc networks

WACNet - Wireless Ad-hoc Community Network

Multi-routing schemes for ad-hoc wireless networks

Space-time block coding for wireless ad hoc networks

Routing algorithms on wireless multihop networks and their modifications

A fast and low-power distance computation unit dedicated to neural networks, based on redundant arithmetic

Energy-efficient skewed static logic design with dual Vt

Short-circuit power analysis of an inverter driving an RLC load

A 1-V 2.4-GHz CMOS LNA with source degeneration as image-rejection notch filter

Graph problems in multi-hop networks

A circuit-connection-based multihop wireless infrastructure for local communities

Pipeline architecture for DCT/IDCT

An efficient technique for error-free algebraic-integer encoding for high performance implementation of the DCT and IDCT

A pipelined dataflow small micro-coded asynchronous processor and its application to DCT

An efficient 2-D DWT architecture via resource cycling

An LSI for V/sub DD/-hopping and MPEG4 system based on the chip

Cache energy reduction by dual voltage supply

Power modeling and low-power design of content addressable memories

A fast self-convergent flash-memory programming scheme for MV and analog data storage

An application specific multi-port RAM cell circuit for register renaming units in high speed microprocessors

New current-mode sense amplifiers for high density DRAM and PIM architectures

Volume 3 - 2001

Volume 2 - 2001

Volume 1 - 2001

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349)

ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)

Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97

1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96

Proceedings of ISCAS'95 - International Symposium on Circuits and Systems

Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94

1993 IEEE International Symposium on Circuits and Systems

[Proceedings] 1992 IEEE International Symposium on Circuits and Systems

1991., IEEE International Sympoisum on Circuits and Systems

IEEE International Symposium on Circuits and Systems

IEEE International Symposium on Circuits and Systems,

1988., IEEE International Symposium on Circuits and Systems

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