NDLI: The matching of small capacitors for analog VLSI

Content Provider	IEEE Xplore Digital Library
Author	Minch, B.A. Diorio, C. Hasler, P. Mead, C.
Copyright Year	1996
Description	Author affiliation: Comput. & Neural Syst. Program, California Inst. of Technol., Pasadena, CA, USA (Minch, B.A.; Diorio, C.; Hasler, P.; Mead, C.)
Abstract	The capacitor has become the dominant passive component for analog circuits designed in standard CMOS processes. Thus, capacitor matching is a primary factor in determining the precision of many analog circuit techniques. In this paper, we present experimental measurements of the mismatch between square capacitors ranging in size from 6 /spl mu/m/spl times/6 /spl mu/m to 20 /spl mu/m/spl times/20 /spl mu/m fabricated in a standard 2 /spl mu/m double-poly CMOS process available through MOSIS. For a size of 6 /spl mu/m/spl times/6 /spl mu/m, we have found that those capacitors that fell within one standard deviation of the mean matched to better than 1%. For the 20 /spl mu/m/spl times/20 /spl mu/m size, we observed that those capacitors that fell within 1 standard deviation of the mean matched to about 0.2%. Finally, we observed the effect of nonidentical surrounds on capacitor matching.
Starting Page	239
Ending Page	241
File Size	275205
Page Count	3
File Format	PDF
ISBN	0780330730
DOI	10.1109/ISCAS.1996.539873
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-05-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Analog circuits Voltage control Capacitance measurement CMOS process Switched capacitor circuits MOSFETs Threshold voltage Proportional control Analog computers
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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