NDLI: A dynamic reconfigurable clock generator

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15th Annual IEEE International ASIC/SOC Conference

Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558)

Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558)

VLSI implementation of high performance burst mode for 128-bit block ciphers

An auditory classifier employing a wavelet neural network implemented in a digital design

Performance evaluation of 3rd order sigma-delta (/spl Sigma/-/spl utri/) modulators via FPGA implementation

Light and sound data fusion in analog VLSI

Current-sensing for crossbars

Demonstration of power enhancements on an industrial circuit through delay management of non-critical data paths

Efficient gate clustering for MTCMOS circuits

Gate-diffusion input (GDI)-a novel power efficient method for digital circuits: a design methodology

ASIC and DSP implementation of channel filter for 3G wireless TDD system

A mobile station modem VLSI for CDMA2000-1x

WCDMA receiver architecture with unique frequency plan

Code verification by hardware acceleration

Vector Language: a proposed verification methodology for intellectual-property cores

The use of SystemC for design verification and integration test of IP-cores

Algorithm, architecture, and implementation of algorithmic delay-locked loop based data recovery circuit for high-speed serial data communication

A new 246 MHz active LC band-pass filter for IF sub-sampling GSM receivers

A low-noise fast-settling PLL with extended loop bandwidth enhancement by new adaptation technique

On-chip RF filters using bond wire inductors

Direct-mapped asynchronous finite-state machines in CMOS technology

A socket interface for GALS using locally dynamic voltage scaling for rate-adaptive energy saving

MCSoC: a platform for clock managed systems on a chip

Integrated approach to optimized code generation for heterogeneous-register architectures with multiple data-memory banks

Input controlled refresh for noise tolerant dynamic circuits

A low-phase-noise CMOS ring oscillator with differential control and quadrature outputs

A novel all digital phase locked loop (ADPLL) with ultra fast locked time and high oscillation frequency

A stochastic global net-length distribution for a three-dimensional system-on-a-chip (3D-SoC)

A practical approach to DSM repeater insertion: satisfying delay constraints while minimizing area and power

A new two-layer power/ground router for VLSI layout

Estimating interconnect wirelength for soft IP

An embedded programmable core for the implementation of high performance digital filters

Cell designs for self-timed FPGAs

Reprogrammable processing capabilities of embedded FPGA blocks

Low-power constant-coefficient multiplier generator

Block-based multi-period refresh for energy efficient dynamic memory

A novel low power CAM design

On the low-power design of DCT and IDCT for low bit-rate video codecs

An improved pass-gate adiabatic logic

Reuse of addressable system bus for SOC testing

Model reduction based on value dependency

FSimGEO: a test generation method for path delay fault test using fault simulation and genetic optimization

Design verification and DFT for an embedded reconfigurable low-power multiplier in system-on-chip applications

A flexible approach to the design of complex embedded systems

Multi-way clustering techniques for system level partitioning

A clustering utility based approach for ASIC design

Structured object composition for system modeling

An efficient ABR service engine for ATM network

SoC integration of digital audio applications using protocol compiler and ATMEL FPSLIC

A low power FIR filtering core

A CMOS dual-modulus prescaler based on a new charge sharing free D-flip-flop

Optimum sigma-delta (/spl Sigma/-/spl Delta/) de-modulator filter implementation via FPGA

Modular scalable parallel architectures for fast transforms

Network processor design for optical burst switched networks

Testing for AMBA/sup TM/ compliance

Comparative cost/performance evaluation of digit-serial multipliers for finite fields of type GF(2/sup n/)

A unified validation methodology for system level co-design and co-implementation

A VLSI design of a high-speed Reed-Solomon decoder

Dual mode transmitter with adaptively controlled slew rate and impedance supporting wide range data rates

Circuit challenges and proposed solutions targeting nanometer technologies

A dynamic reconfigurable clock generator

SCALIP - a scalable IP solution for pipelined arrays with limited feedback

Integrated scheduling and register assignment for VLIW-DSP architectures

VLSI Reed Solomon decoder architecture for networked multimedia applications

A true block pipelined programmable Reed-Solomon CODEC for high-speed/low-power applications

Digit-serial multiplier design using skew-tolerant domino circuits

An efficient digit-serial systolic multiplier for finite fields GF(2/sup m/)

Design of a reusable memory management system

A high-speed multi-port data buffer design for low-energy DSP applications

I/O design considerations for multi-application circuits

Sample integrated Fourier transform (SIFT): a novel real-time process

CID/DRAM mixed-signal parallel distributed array processor

A new sensing and digital-conversion scheme with adaptive image-quality adjustment for a fingerprint sensor chip

Reducing the cost of scan in deep sub-micron designs

IP protection for VLSI designs via watermarking of routes

Re-useable hardware/software co-verification of IP blocks

Flexible IP blocks for customized synthesis

Design methods for SOC control CODECS to enhance reuse

A hierarchical simulation framework for application development on system-on-chip architectures

Noise-aware design for ESD reliability in mixed-signal integrated circuits

Global routing methodology for analog and mixed-signal layout

Evaluating the impact of architectural-level optimizations on clock power

Future-ready ultrafast 8bit CMOS ADC for system-on-chip applications

A low-power variable resolution analog-to-digital converter

A low-voltage switched-current memory cell based delta sigma modulator

Low-voltage switched-current circuits for mixed signal systems

Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541)

Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454)

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in