NDLI: BiCMOS ASICs: technology and applications

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Third Annual IEEE Proceedings on ASIC Seminar and Exhibit

Proceedings. Third Annual IEEE ASIC Seminar and Exhibit (Cat. No.90TH0303-8)

ASIC's for cellular mobile telephones (CMT's)

ASIC synthesis cost model

New rules, new markets, new skills: ASICS in the 90s

Qualified manufacturer's list (QML)-a new approach for qualifying ASICs

ASIC applications in diagnostic imaging systems

Fault-tolerant design of VLSI circuits and systems

Elements of VHDL for description of hardware: a tutorial view

Simulation techniques for VLSI circuits

An overview of the design methods and tools used in bipolar analog arrays

Logic synthesis in a CAE design environment-a tutorial

Modeling and simulation with Saber

BiCMOS ASICs: technology and applications

The realities of ASIC packaging

Modeling and simulation methods for mixed signal circuit simulation

Affordable ASIC design

Putting the designer in control with desktop prototyping

Managing ASIC projects

An economic comparison of telecommunication system design costs utilizing a modular design approach

Partitioning systems into ASICs

Quick turn around ASIC size estimation and tradeoff for new designs and technology migration using user driven careabouts

Cost benefit tradeoffs for ASIC versus programmable logic device

A common design and test strategy for merchant ASICs

Managing risk in ASIC design cycle

Configurable demodulator ASIC for the TDRSS communication system

A SONET telecom system block library for ASIC design

A complete VLSI treatment for the LAPD protocol (ISDN level 2)

Putting it all together: using automated techniques for the design and test of large telecommunication devices

Superintegrated smart access controller

ASIC design in a next generation workstation

Case study of a high speed three-dimensional graphics chip set

Spread spectrum pre-processor ASIC design: a case study

Testability features in a high-density memory module

A development system for an SRAM-based user-reprogrammable gate array

BiCMOS submicron compiler memories

An efficient ASIC design of a content-addressable memory (CAM)

1 K*128 high-performance, low power configurable CMOS SRAM compiler

A high performance memory compiler for multi-port RAMs

The microelectronic device selection process

Systems engineering: a summary of electronics packaging techniques available for present and future systems

'VHSIC' technology from a merchant ASIC supplier

The architecture constraints in test equipment designs

ASIC technology and the selection of processors for DoD systems

Mixed-level simulation with a Zycad simulation engine

Logic cell emulation for ASIC in-circuit emulators

A validation strategy for embedded core ASICs

Efficient timing analysis for general synchronous and asynchronous circuits

SPIL-a program to automatically create ASIC macro models for logic simulation

UNI-MOS: a unified SPICE built-in MOSFET model for circuit simulation and lifetime evaluation

Modeling strategy for post layout verification

Designing a VLSI microprocessor for emulation

Synchronous design: the right technique for digital ASICs

A solution to mapping an ASIC design hierarchy into an efficient block-place-and-route layout hierarchy

The incremental versus the conventional approach to ASIC development-why use MOSIS to develop ASIC?

Matching ASIC design methodologies to the manufacturing environment

An AI approach to timing analysis and optimization for standard cell based ASICs

Quick turn around time ASIC design using KBSC

NetList/sup +/: a simple language for fast ASIC prototyping

FORESIGHT: a fast turn-around and low cost ASIC prototyping alternative

Design system for special purpose processor executing algorithms described by higher level language

An ASIC digital motion control unit

An efficient two-dimensional pipeline architecture for digital signal processing operation

A parameterizable biquad clock for IIR filters in ASICs: implementations and motivations

An 8*8 discrete cosine transform chip with pixel rate clocks

A pipelined ASIC for color matrixing and convolution

Simulation considerations for analog-digital ASICs

Mixed-signal ASIC simulation via an analog modeling package

Autonomous test scheme for analog ASICs

Mixed analog/digital in a mixed bipolar/MOS technology

A 200 MHz 100 K ECL output buffer for CMOS ASICs

A novel programmable gain amplifier

Oversampled A/D and D/A converters for VLSI system integration

Hierarchical test generation for ASIC circuits using macro specification

JTAG and Hitachi's autodiagnosis

Design trade-offs when implementing boundary scan in an application specific integrated circuit

Designing IEEE 1149.1 compatible boundary-scan logic into an ASIC using Texas Instrument's Scope architecture

Reliability, testability and yield of majority voting VLSI

Design and test strategy for differential cascode voltage switch circuits

ASIC education at Tampere University of Technology

Rapid prototyping, is there an educational dilemma? (ASIC design)

KUE-CHIP: a microprocessor for education of computer architecture and LSI design

Development of an ASIC macrocell design CAD system

A unified macro CAD system

A PC based CAD system for an analog/digital CMOS/DMOS/bipolar/smart power array

Automated CAE tools for full custom design of bipolar analog ASICs

An integrated geometric driven bipolar analog/digital standard cell and semi custom design environment

An automated, structured layout methodology for staggered pad, I/O-bound ASIC design

Impact of parameterization on the design of module generators

Behavioral models of ASIC VLSI cells

Design methodology for a 1.0 mu cell-based library efficiently optimized for speed and area

Automatic characterization and modeling (ASIC design)

Characterizing a cell library using iCCS (ASIC design)

Validating an ASIC standard cell library

Automated maintenance of ASIC libraries in a dynamic design environment

Direct access test scheme-implementation and verification in embedded ASIC designs

Interfacing test equipment to high density chip-on-tape

Characterization of ASIC performance via application specific test engineering

An assembler approach to the automation of test vector generation

ASIC VLSI design and development in MOSart-a focus on logic analysis and automated test vector generation

Hardware emulation of VLSI designs

DFT standards allow optimized tester configuration to reduce cost of test

Designing IEEE Std 1149.1 into your semiconductor products

QRS/BIST: a reliable heart rate monitor ASIC

Electronic remote identification-a case study

System designer's realization of a core-based ASIC in a comfortable environment (microcontrollers)

An Intel 18253 ASIC chip design

Multi circular buffer controller chip for advanced ESM system

ASIC design and analysis using the system design synthesis tool: four case studies

Metastability-a designer's viewpoint

A cost effective way to test embedded RAM and ROM

BiCMOS ASIC trends-from a systems perspective

Fast ECL-to-CMOS and CMOS-to-ECL translators for an 0.8 mu m BiCMOS gate array

Third-generation architecture boosts speed and density of field-programmable gate arrays

AMD's MACH family breaks PLD speed and density barrier

Re-targetting manufacturing technologies in multichip module layout

Templates for synthesis from VHDL

PLASMA: a FSM design kernel

The ideal multiplier compiler

GRCA: a global approach for floorplanning synthesis

Economic implications of logic synthesis

Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,

BiCMOS ASICs: technology and applications

Content Provider	IEEE Xplore Digital Library
Author	Wong, T.
Copyright Year	1990
Description	Author affiliation: Semicond. & I.C. Div., Hitachi America Ltd., Brisbane, CA, USA (Wong, T.)
Abstract	It is pointed out that although higher speed and lower power dissipation allow BiCMOS to compete with CMOS and ECL devices, CMOS continues to be the choice for large density, low-power, and cost-sensitive application, and ECL remains the preferred choice for very-high-speed medium-density applications. The latter include cache static RAM, telecom, and interface chips between CMOS and fast ECL and TTL memory. BiCMOS now offers system designers an important bridge between power-hungry ECL and high-density CMOS. BiCMOS SRAMs are the most well-known type of high-performance BiCMOS devices. In addition to SRAMS, BiCMOS DRAMs have also been introduced. BiCMOS gate arrays find widespread acceptance in applications such as high-end personal computers, laser printers, workstations, mini-supers, and telecommunications. A relatively new application for BiCMOS technology is in the area of RISC CPUs.<>
File Size	329944
File Format	PDF
DOI	10.1109/ASIC.1990.186081
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-09-17
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	BiCMOS integrated circuits CMOS technology Random access memory Application software Power dissipation Read-write memory Telecommunications Bridges Optical arrays Microcomputers
Content Type	Text
Resource Type	Article

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