NDLI: Creation of an undergraduate curriculum in ASIC design

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Third Annual IEEE Proceedings on ASIC Seminar and Exhibit

Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,

ASIC design for testability

Introduction to CMOS analog standard cell ASIC design

Mixed signal ASIC design issues and methodologies

Fault simulation basics

BiCMOS ASICs: technology and applications

Design automation: pre-layout design verification and design submission for BiCMOS ASIC arrays

Level synthesis approach to application-specific integrated circuits (ASIC) design

Application-specific array processors

GaAs ASIC technology

GaAs ASIC design case study

High density and high performance ECL: some design tips

ECL ASIC, a practical choice of high performance systems

Choosing a design center

Design of integrated circuits for electronic imaging applications

Trends in ECL array technology

Perspective on BiCMOS

A 1856 I/O cell CMOS SOG with half-ns clock skew and a 6 ns RAM

Performance analysis of a BiNMOS device

A case study of functional design using functional simulation and logic synthesis

Integrating logic synthesis into a full chip ASIC design system

The development of application specific integrated circuits using the System Design Synthesis Tool

Neural network development using VHDL

A new language suite for designer-specifiable ASIC cell compilers

A high throughput, asynchronous, dual port FIFO memory implemented in ASIC technology

High performance CMOS dual-port SRAM compiler

A single-polysilicon flip-flop EEPROM for ASIC application

A 1.3 mu m BiCMOS gate array with configurable on-chip 3-port RAM

ECL and BiCMOS application specific memories (ASMs) on a single chip

IEEE-1149.1 use in design for verification and testability at Texas Instruments

Design test-flexible, efficient, and thorough solutions to overcome simulation-to-test roadblocks

Applying testability to an ASIC architectural core

Test considerations for mixed analog and digital ASICs

A gate array designed with built in testability

Test generation for multiple stuck-open faults in CMOS logic circuits

A GaAs 600 Mbit/s 24B1P coder/decoder ASIC

ECL and CMOS ASICs for time-to-digital conversion

SPHINX-a VLSI processing element chip for pyramid computer

Implications of a new architectural approach to designing ECL megacells

Custom RISC has international applications

Automation of core-based design construction

Electrical design rule checker for core and block based ASIC designs

DSP core with parallel module testability

In-circuit-emulation in ASIC architectural core designs

The realities of core based ASIC design: a single-loop industrial process controller

PIMM1, an image processing ASIC based on mathematical morphology

Design automation system and architecture for high-performance integer applications

ASIC design of digital ECG filter

A 25 MOPS systolic integer divider IC

Case study: an NTSC imaging system timing gate array design

A network access interface ASIC for a cross-connect system

PC/AT-compatible devices: fewer is better

An integrated circuit for texture distance computation

ASIC replacement for an SSI component design-a case study

Predicting and scaling power consumption in CMOS ASICs

Fault grading operational self-test

Fault grading, a measure of logic simulation integrity

Incremental netlist compilation for IKOS hardware logic simulator

Ground bounce in CMOS ASICs

A circuit simulation model of submicron MOSFETs for SPICE

Wide-band analog CMOS circuits at intermediate frequencies

Analog macrocell layout generation

Synthesis of analog ASICs using optimization in conjunction with circuit simulation techniques

A CMOS micropower heart rate indicator

Heuristic issues in analog IC design

ASIC design project scheduling

Painless ASIC design in the system environment

Custom cell development for standard cell designs

Key to a successful cell library development: design methodology

High performance compilers for ASIC designs

A user-configurable RAM compiler for gate arrays

Zygen timing model generator

OASYS: a framework for analog circuit synthesis

An analog module generator that includes operational sensitivities

Composite device model enhances worst case simulation of bipolar analog ASICs

Predictive analysis of sensitivity to chip-routing parasitics

The integration of power supply components within standard cell integration circuits

Creation of an undergraduate curriculum in ASIC design

A university flexible technology foundry for VLSI application specific integrated circuits

Automated schematic capture and the UCS51 (microcontroller)

ASIC technical training-the challenges and opportunities

Path-programmable logic

Proceedings: The Second Annual IEEE ASIC Seminar and Exhibit (Cat. No.89TH0280-8)

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