NDLI: Interfacing FPGA/VLSI processor arrays

Content Provider	IEEE Xplore Digital Library
Author	Fernando, J. Jean, J.
Copyright Year	1995
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Wright State Univ., Dayton, OH, USA (Fernando, J.; Jean, J.)
Abstract	Mapping DSP algorithms to FPGA/VLSI circuits is an important issue in Application-Specific Array Processor design. Since a DSP algorithm can be abstracted as a graph where each node is a shift-invariant DG (Dependence Graph) and the edges denote the data flow, it is possible to map a DSP algorithm to a set of processor arrays with some interface circuits. The interface design depends on the projection/scheduling vectors used on the two corresponding shift-invariant DGs and the interfacing cost is very significant when a lot of delays are necessary or when the processor operations are relatively inexpensive in terms of area. Therefore, when selecting these vectors in a design environment, the effect on the interface circuit must be accurately computed. In this paper, various interface circuit designs are presented and categorized based on the data conversion requirement. An algorithm to select a design from many design options to minimize the cost is also described.
Starting Page	230
Ending Page	237
File Size	482837
Page Count	8
File Format	PDF
ISBN	0818671092
ISSN	10636862
DOI	10.1109/ASAP.1995.522927
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-07-24
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Very large scale integration Digital signal processing Circuits Algorithm design and analysis Costs Process design Flow graphs Processor scheduling Delay
Content Type	Text
Resource Type	Article
Subject	Computer Networks and Communications Hardware and Architecture

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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