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Logic Built-in Self-test of An Electronic Circuit
| Content Provider | The Lens |
|---|---|
| Description | Outil permettant de réaliser un auto-test intégré logique d'un circuit électronique fonctionnant en fonction d'un cycle d'horloge. L'outil stocke une signature de test configurable dans une mémoire à accès aléatoire conjointement avec un compteur de motif pour un motif de test, un nombre d'au moins un registre de signature supplémentaire correspondant à un nombre d'entrées dans la mémoire à accès aléatoire. L'outil détermine une erreur en fonction, au moins en partie, d'une opération de comparaison pour un motif de test donné, l'opération de comparaison déterminant si la signature de test dans le premier registre de signature avant un cycle de capture d'un motif de test suivant diffère de la signature de test configurable correspondante. L'outil stocke l'erreur dans un registre de signature supplémentaire correspondant. |
| Abstract | A tool for performing a logic built-in self-test of an electronic circuit operating on a clock cycle basis. The tool stores a configurable test signature in a random-access memory together with a pattern counter for a test pattern, wherein a number of the at least one additional signature register corresponds to a number of entries in the random access memory. The tool determines an error based, at least in part, on a compare operation for a given test pattern, wherein the compare operation determines whether the test signature in the first signature register before a capture cycle of a next test pattern differs from the corresponding configurable test signature. The tool stores the error in a corresponding additional signature register. |
| Related Links | https://www.lens.org/images/patent/WO/2023007344/A1/WO_2023_007344_A1.pdf |
| Language | English |
| Publisher Date | 2023-02-02 |
| Access Restriction | Open |
| Alternative Title | Auto-test Intégré Logique D'un Circuit Électronique |
| Content Type | Text |
| Resource Type | Patent |
| Date Applied | 2022-07-25 |
| Agent | Vetter, Svenja |
| Applicant | Ibm Ibm China Invest Co Ltd Ibm Deutschland |
| Application No. | 2022056834 |
| Claim | An apparatus for performing a logic built-in self-test of an electronic circuit operating on a clock cycle basis, wherein the electronic circuit comprises one or more scan chains connected to a multiple input signature register, wherein the multiple input signature register generates test signatures in a first signature register utilizing test patterns generated as input for the one or more scan chains, and a test controller that provides control signals to and receives control signals from the first signature register, the apparatus comprising: a random-access memory, at least one additional signature register, and a logic circuitry; wherein a configurable test signature is stored in the random-access memory together with a pattern counter for a test pattern, wherein a number of the at least one additional signature register corresponds to a number of entries in the random access memory; wherein the logic circuitry is further connected to outputs of the first signature register and to inputs of the at least one additional signature register; wherein the logic circuitry determines an error by performing a compare operation for a given test pattern, the compare operation identifying that the test signature in the first signature register before a capture cycle of a next test pattern differs from the corresponding configurable test signature; and wherein the logic circuitry stores the error in a corresponding additional signature register. The apparatus of claim 1, wherein the compare operation is an XOR operation. The apparatus of claim 1 or 2, wherein the logic circuitry is configured to receive control signals from and to provide control signals to the test controller, wherein the test controller is configured to receive control signals from and provide control signals to the logic circuitry. The apparatus of any of the previous claims, wherein the logic circuitry is adapted for loading a current error in a failed test pattern, wherein the current error is calculated by using the compare operation on previous signatures of failed test patterns stored in the additional signature register, and the additional signature register is initialized with the current error. The apparatus of any of the previous claims, wherein the first signature register and/or the additional signature register are configured to generate test signatures from automatically generated test patterns by implementing a linear function depending on a generator polynomial for a given number of clock cycles. The apparatus of any of the previous claims, further configured to compact test patterns independently for generating the test signatures. The apparatus of any of the previous claims, wherein the electronic circuit further comprises a number of additional signature registers corresponding to a maximum number of faults to be identified by a self-test. The apparatus of any of the previous claims, wherein the logic circuitry is implemented as a finite state machine. The apparatus of claim 8, wherein the logic circuitry is configured to be triggered by the test controller using a loop counter counting how many patterns have been applied and a capture signal specifying whether to apply a system clock or a scan clock. The apparatus of claim 8, wherein the logic circuitry is configured to, upon being triggered, update the additional signature register with a corresponding error. A method for performing a logic built-in self-test of an electronic circuit operating on a clock cycle basis, wherein the electronic circuit comprises one or more scan chains connected to a multiple input signature register, wherein the multiple input signature register generates test signatures in a first signature register utilizing test patterns generated as input for the one or more scan chains, and a test controller that provides control signals to and receives control signals from the first signature register, the method comprising: storing, by one or more computer processors, a configurable test signature in a random-access memory together with a pattern counter for a test pattern, wherein a number of the at least one additional signature register corresponds to a number of entries in the random access memory; determining, by the one or more computer processors, an error based, at least in part, on a compare operation for a given test pattern, wherein the compare operation determines whether the test signature in the first signature register before a capture cycle of a next test pattern differs from the corresponding configurable test signature; and storing, by the one or more computer processors, the error in a corresponding additional signature register. The method of claim 11, wherein the compare operation is an XOR operation. The method of claim 11 or 12, further comprising: performing, by the one or more computer processors, interval-based testing to identify a first failing test pattern with a first pattern count and the corresponding configurable signature for this test pattern; configuring, by the one or more computer processors, the additional signature register with the corresponding error; applying, by the one or more computer processors, testing until a second pattern count which is greater than the first pattern count is reached; and responsive to a determination that the test signature in the first signature register combined with the signature stored in the additional signature register using the compare operation differs from the configurable signature for the second pattern count, adjusting, by the one or more computer processors, the second pattern count and repeating testing until a next failing test pattern is found. The method of any one of the claims 11 to 13, further comprising: combining, by the one or more computer processors, for a first pattern count of a first failing test pattern, the test signature of the first signature register with the corresponding configurable signature using the compare operation and feeding the result to the corresponding additional signature register; combining, by the one or more computer processors, for a second pattern count of a next failing test pattern, the test signature of the first signature register with the corresponding configurable signature using the compare operation; combining, by the one or more computer processors, a result with the content of the additional signature register for the first failing test pattern using the compare operation and feeding the result to the corresponding second register; and combining, by the one or more computer processors, the test signature of the first signature register for the test patterns with the contents of the additional registers of previous failing test pattern counts using compare operations until a test pattern with a corresponding fault-free signature is passed without a fault. The method of any one of the claims 11 to 14, further comprising: triggering, by the one or more computer processors, a test controller with a loop counter to count how many patterns have been applied and a capture signal specifying whether to apply a system clock or a scan clock. The method of any one of the claims 11 to 15, further comprising: updating, by the one or more computer processors, the additional signature register with the corresponding error. The method of any one of the claims 11 to 16, further comprising: calculating, by the one or more computer processors, a current error in a failed test pattern using the compare operation on previous signatures of failed test patterns stored in the additional signature registers and initializing the additional signature register with the current error. The method of any one of the claims 11 to 17, further comprising: checking, by the one or more computer processors, completion of the logic built-in self-test for an additional fault by aggregating the additional signature registers with the first signature register and comparing the resulting signature with a fault free signature. A computer program product for performing a logic built-in self-test of an electronic circuit operating on a clock cycle basis, wherein the electronic circuit comprises one or more scan chains connected to a multiple input signature register, wherein the multiple input signature register generates test signatures in a first signature register utilizing test patterns generated as input for the one or more scan chains, and a test controller that provides control signals to and receives control signals from the first signature register, the computer program product comprising: one or more computer readable storage media and program instructions stored on the one or more computer readable storage media, the stored program instructions comprising: program instructions to store a configurable test signature in a random-access memory together with a pattern counter for a test pattern, wherein a number of the at least one additional signature register corresponds to a number of entries in the random access memory; program instructions to determine, an error based, at least in part, on a compare operation for a given test pattern, wherein the compare operation determines whether the test signature in the first signature register before a capture cycle of a next test pattern differs from the corresponding configurable test signature; and program instructions to store the error in a corresponding additional signature register. The computer program product of claim 19, further comprising: program instructions to perform interval-based testing to identify a first failing test pattern with a first pattern count and the corresponding configurable signature for this test pattern; program instructions to configure the additional signature register with the corresponding error; program instructions to apply testing until a second pattern count which is greater than the first pattern count is reached; and program instructions to, responsive to a determination that the test signature in the first signature register combined with the signature stored in the additional signature register using the compare operation differs from the configurable signature for the second pattern count, adjust the second pattern count and repeating testing until a next failing test pattern is found. |
| CPC Classification | STATIC STORES Measuring Electric Variables;Measuring Magnetic Variables ELECTRIC DIGITAL DATA PROCESSING |
| Extended Family | 034-922-855-197-238 089-866-379-806-937 183-158-499-326-41X |
| Patent ID | 2023007344 |
| Inventor/Author | Cook Lobo Alejandro Gentner Thomas Kugel Michael Torreiter Otto |
| IPC | G01R31/3183 G01R31/3177 |
| Status | Pending |
| Simple Family | 034-922-855-197-238 089-866-379-806-937 183-158-499-326-41X |
| CPC (with Group) | G11C29/44 G01R31/318566 G06F11/27 G11C29/16 G11C29/32 G11C29/36 G11C29/38 G01R31/3177 |
| Issuing Authority | World Intellectual Property Organization (WIPO) |
| Kind | Patent Application Publication |
