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Author Habekotte, E. ♦ Stallman, J.
Sponsorship IEEE Solid-State Circuits Society ♦ IEEE Electron Devices Society ♦ IEEE Circuits and Systems Society ♦ IEEE Electron Devices Society ♦ IEEE Solid-State Circuits Society ♦ IEEE Solid-State Circuits Society ♦ Japan Society of Applied Physics (JSAP) ♦ IEEE Solid-State Circuits Society ♦ IEEE Solid-State Circuits Society ♦ IEEE Microwave Theory and Techniques Society ♦ IEEE Solid-State Circuits Society ♦ IEEE San Francisco Section ♦ Bay Area Council ♦ Univ. PA ♦ IEEE
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1966
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Switches ♦ Voltage control ♦ Power dissipation ♦ CMOS technology ♦ Pulsed power supplies ♦ Flip-flops ♦ Isolation technology ♦ Plasma displays ♦ Frequency ♦ Clocks
Description Several flip-flop control configurations for the coplanar CMOS power switch are proposed that lead to a reduction of the on-chip power dissipation and input control voltage. Moreover, the switch becomes less sensitive to tolerances in the capacitive voltage divider controlling the gate of the output transistor. An acceptable tradeoff between chip area consumed by the flip-flop arrangement, reduction of the on-chip power dissipation, and input control voltage is possible. The on-chip low-voltage control circuitry is also described.
ISSN 00189200
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1984-02-01
Publisher Place U.S.A.
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Volume Number 19
Issue Number 1
Size (in Bytes) 1.11 MB
Page Count 8
Starting Page 147
Ending Page 154


Source: IEEE Xplore Digital Library