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Author Patnaik, Milan ♦ Chidhambaranathan, R ♦ Garg, Chirag ♦ Roy, Arnab ♦ Devanathan, V. R. ♦ Balachandran, Shankar ♦ Kamakoti, V.
Source ACM Digital Library
Content type Text
Publisher Association for Computing Machinery (ACM)
File Format PDF
Copyright Year ©2015
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword 3D chip multi-processor ♦ Thermal and power management ♦ Adaptive body bias ♦ Delay and power modeling ♦ Finite horizon control ♦ Frequency governors ♦ Model predictive control ♦ Task allocation ♦ Temperature-ware scheduling ♦ Voltage assignment
Abstract With the increase in process variations and diversity in workloads, it is imperative to holistically explore optimization techniques for power and temperature from the circuit layer right up to the compiler/operating system (OS) layer. This article proposes one such holistic technique, called proactive workload aware temperature management framework for low-power chip multi-processors (ProWATCh). At the compiler level ProWATCh includes two techniques: (1) a novel compiler design for estimating the architectural parameters of a task at compile time; and (2) a model-based technique for dynamic estimation of architectural parameters at runtime. At the OS level ProWATCh integrates two techniques: (1) a workload- and temperature-aware process manager for dynamic distribution of tasks to different cores; and (2) a model predictive control-based task scheduler for generating the efficient sequence of task execution. At the circuit level ProWATCh implements either of two techniques: (1) a workload-aware voltage manager for dynamic supply and body bias voltage assignment for a given frequency in processors that support adaptive body bias (ABB); or (2) a workload-aware frequency governor for efficient assignment of upper and lower frequency bounds for frequency scaling in processors that do not support an ABB. Employing ProWATCh (with voltage manager) on an ABB-compatible 3D OpenSPARC architecture using $\textit{MiBench}$ benchmarks resulted in an average $\textbf{18%}$ $(\textbf{19ˆC})$ reduction in peak temperature. Evaluating ProWATCh on an existing quad-core Intel Corei7 processor with frequency governor alone (as the processor does not support an ABB interface) resulted in $\textbf{10%}$ $(\textbf{8ˆC})$ reduction in peak temperature when compared to what was obtained using the native Linux 3.0 completely fair scheduler (CFS). To study the effectiveness of the proposed framework across benchmark suites, ProWATCh was evaluated on a quad-core Intel Corei7 processor using CPU SPEC 2006 benchmarks which resulted in $\textbf{7ˆC}$ reduction in peak temperature as compared to the native Linux 3.0 CFS.
Description Author Affiliation: Texas Instruments Ltd, Bengaluru, India (Devanathan, V R); Indian Institute of Technology Madras, Chennai, India (Patnaik, Milan; Chidhambaranathan, R.; Garg, Chirag; Roy, Arnab; Balachandran, Shankar; Kamakoti, V.)
ISSN 15504832
Age Range 18 to 22 years ♦ above 22 year
Educational Use Research
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2015-09-01
Publisher Place New York
e-ISSN 15504840
Journal ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume Number 12
Issue Number 3
Page Count 25
Starting Page 1
Ending Page 25

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Source: ACM Digital Library