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Author Prieto, Manuel ♦ Sáez, Juan Carlos ♦ Chaver, Daniel ♦ Castro, Fernando
Source ACM Digital Library
Content type Text
Publisher Association for Computing Machinery (ACM)
File Format PDF
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Asymmetric multicore ♦ Operating systems ♦ Scheduling
Abstract Symmetric-ISA (instruction set architecture) asymmetric-performance multicore processors (AMPs) were shown to deliver higher performance per watt and area than symmetric CMPs for applications with diverse architectural requirements. So, it is likely that future multicore processors will combine big power-hungry fast cores and small low-power slow ones. In this paper, we propose a novel thread scheduling algorithm that aims to improve the throughput-fairness trade-off on AMP systems. Our experimental evaluation on real hardware and using scheduler implementations on a general-purpose operating system, reveals that our proposal delivers a better throughput-fairness trade-off than previous schedulers for a wide variety of multi-application workloads including single-threaded and multithreaded applications.
Description Affiliation: Complutense University of Madrid, Madrid, Spain (Sáez, Juan Carlos; Castro, Fernando; Chaver, Daniel; Prieto, Manuel)
Age Range 18 to 22 years ♦ above 22 year
Educational Use Research
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2014-01-10
Publisher Place New York
Journal ACM SIGMETRICS Performance Evaluation Review (PERV)
Volume Number 41
Issue Number 1
Page Count 2
Starting Page 343
Ending Page 344


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Source: ACM Digital Library