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Author Sampson, Jack ♦ Swaminathan, Karthik ♦ Liu, Huichu ♦ Narayanan, Vijaykrishnan
Source ACM Digital Library
Content type Text
Publisher Association for Computing Machinery (ACM)
File Format PDF
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Abstract For any given application, there is an optimal throughput point in the space of per-processor performance and the number of such processors given to that application. However, due to thermal, yield, and other constraints, not all of these optimal points can plausibly be constructed with a given technology. In this paper, we look at how emerging steep slope devices, 3D circuit integration, and trends in process technology scaling will combine to shift the boundaries of both attainable performance, and the optimal set of technologies to employ to achieve it. We propose a heterogeneous-technology 3D architecture capable of operating efficiently at an expanded number of points in this larger design space and devise a heterogeneity and thermal aware scheduling algorithm to exploit its potential. Our heterogeneous mapping techniques are capable of producing speedups ranging from 17% for a high end server workloads running at around 90°C to over 160% for embedded systems running below 60°C
Description Affiliation: The Pennsylvania State University (Swaminathan, Karthik; Liu, Huichu; Sampson, Jack; Narayanan, Vijaykrishnan)
Age Range 18 to 22 years ♦ above 22 year
Educational Use Research
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1981-04-01
Publisher Place New York
Journal ACM SIGARCH Computer Architecture News (CARN)
Volume Number 42
Issue Number 3
Page Count 12
Starting Page 241
Ending Page 252

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Source: ACM Digital Library