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Author Skala, K. ♦ Nicoud, J. D.
Source ACM Digital Library
Content type Text
Publisher Association for Computing Machinery (ACM)
File Format PDF
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Abstract In order to build lower cost multimicroprocessor systems, a narrow synchronous bus (15 active lines) is proposed. It multiplexes address and data on 8 bits, and arbitrates in two pipe-lined cycles on four lines. Due to the 20 to 40 MHz bus clock, and the pipelined control logic, the performances are equivalent to Multibus-2, IEEE-P896 and similar 32-bit buses.For the implementation, cards are disposed radially around a special connector. The very short connections allows for the usage of fast HC-MOS drivers with only a light adaptation.
Description Affiliation: Swiss Federal Institute of Technology, Av, de Cour 37, CH-1007 Lausanne (Nicoud, J. D.; Skala, K.)
Age Range 18 to 22 years ♦ above 22 year
Educational Use Research
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1981-04-01
Publisher Place New York
Journal ACM SIGARCH Computer Architecture News (CARN)
Volume Number 14
Issue Number 2
Page Count 6
Starting Page 169
Ending Page 174

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Source: ACM Digital Library