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Author Bakka, Bjørn O. ♦ Bugge, Håkon O. ♦ Kristiansen, Ernst H.
Source ACM Digital Library
Content type Text
Publisher Association for Computing Machinery (ACM)
File Format PDF
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Abstract Two-level cache hierarchies will be a design issue in future high-performance CPUs. In this paper we evaluate various metrics for data cache* designs. We discuss both one- and two-level cache hierarchies. Our target is a new 100+ mips CPU, but the methods are applicable to any cache design. The basis of our work is a new trace-driven, multiprocess cache simulator. The simulator incorporates a simple priority-based scheduler which controls the execution of the processes. The scheduler blocks a process when a system call is executed. A workload consists of a total of 60 processes, distributed among seven unique programs with about nine instances each. We discuss two open bus systems supporting a coherent memory model, Futurebus+ and SCI, as the interconnect system for main memory.
Description Affiliation: Dolphin Server Technology A.S, Oslo, Norway (Bugge, Håkon O.; Kristiansen, Ernst H.; Bakka, Bjørn O.)
Age Range 18 to 22 years ♦ above 22 year
Educational Use Research
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1981-04-01
Publisher Place New York
Journal ACM SIGARCH Computer Architecture News (CARN)
Volume Number 18
Issue Number 2SI
Page Count 10
Starting Page 250
Ending Page 259


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Source: ACM Digital Library