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Author Evans, Joseph B. ♦ Ewy, Benjamin J.
Source ACM Digital Library
Content type Text
Publisher Association for Computing Machinery (ACM)
File Format PDF
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Abstract In this paper we report on a simulation study that examines a uniprocessor system with a three-level memory hierarchy. A simulation model of a single-cycle-per-instruction processor with a small on-chip cache was constructed and tested with various memory hierarchies. The simulation was intended to focus on meeting the demanding requirements of the latest RISC processors such as the MIPS R4000 and the DEC 21064. The simulator used allowed the authors to run traces of hundreds of millions of memory references per case. These long traces gave a more thorough and accurate picture of the memory demands of current processors. Data is presented enabling a designer to incorporate speed estimates based on implementation restrictions into the process of developing memory hierarchies.
Age Range 18 to 22 years ♦ above 22 year
Educational Use Research
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1981-04-01
Publisher Place New York
Journal ACM SIGARCH Computer Architecture News (CARN)
Volume Number 21
Issue Number 3
Page Count 4
Starting Page 34
Ending Page 37


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Source: ACM Digital Library