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Author Choi, Byung-Soo ♦ Van Meter, Rodney
Source ACM Digital Library
Content type Text
Publisher Association for Computing Machinery (ACM)
File Format PDF
Copyright Year ©2012
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword 2D NTC quantum computer architecture ♦ Quantum computer ♦ Quantum adder ♦ Quantum arithmetic algorithms ♦ Quantum circuit
Abstract In this work, we propose an adder for the 2-Dimensional Nearest-Neighbor, Two-Qubit gate, Concurrent (2D NTC) architecture, designed to match the architectural constraints of many quantum computing technologies. The chosen architecture allows the layout of logical qubits in two dimensions with $&sqrt;\textit{n}$ columns where each column has $&sqrt;\textit{n}$ qubits and the concurrent execution of one- and two-qubit gates with nearest-neighbor interaction only. The proposed adder works in three phases. In the first phase, the first column generates the summation output and the other columns do the carry-lookahead operations. In the second phase, these intermediate values are propagated from column to column, preparing for computation of the final carry for each register position. In the last phase, each column, except the first one, generates the summation output using this column-level carry. The depth and the number of qubits of the proposed adder are $Θ(&sqrt;\textit{n})$ and $\textit{O(n)},$ respectively. The proposed adder executes faster than the adders designed for the 1D NTC architecture when the length of the input registers $\textit{n}$ is larger than 51.
ISSN 15504832
Age Range 18 to 22 years ♦ above 22 year
Educational Use Research
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2012-08-01
Publisher Place New York
e-ISSN 15504840
Journal ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume Number 8
Issue Number 3
Page Count 22
Starting Page 1
Ending Page 22

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Source: ACM Digital Library