Access Restriction

Author Bhavsar, D.K. ♦ Poehlman, S.J.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2011
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Arrays ♦ Registers ♦ Testing ♦ Pins ♦ Clocks ♦ Bandwidth ♦ Discrete Fourier transforms
Abstract This paper presents the “t-Ring” based DFX access architecture and the testability features of Intel's latest multi-core Itanium® processor. The architecture solves many common challenges of testing a multi-core CPU using distinctive and innovative solutions. At the core of the architecture is a hierarchical and scalable test access mechanism design providing flexible access for a variety of use models in high volume manufacturing test and debug platforms.
Description Author affiliation: Intel Corporation (Bhavsar, D.K.; Poehlman, S.J.)
ISBN 9781457701535
ISSN 10893539
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2011-09-20
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
e-ISBN 9781457701528
Size (in Bytes) 1.27 MB
Page Count 8
Starting Page 1
Ending Page 8

Source: IEEE Xplore Digital Library