Thumbnail
Access Restriction
Subscribed

Author Cotofana, S. ♦ Juurlink, B. ♦ Vassiliadis, S.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2000
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Counting circuits ♦ Delay ♦ Logic ♦ Decoding ♦ Out of order ♦ Computer aided instruction ♦ Costs ♦ Availability
Abstract New techniques for superscalar instruction issuing are presented. It is shown that the data dependency check for both in-order and out-of-order issuing can be performed in O(log w) gate delay using O(w/sup 2/) primitive gates, where w is the size of the instruction buffer. Furthermore, we present a new counting-based technique for assigning instructions to resources. It requires a delay of O(log w + log m) and an area of O(w/sup 2/log m + mw log k), where m is the number of instruction classes and k is the number of functional units. Finally, we investigate the consequences of executing the data dependency check in parallel with the resource conflict check.
Description Author affiliation: Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands (Cotofana, S.)
ISBN 0769507808
ISSN 10896503
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2000-09-05
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 830.48 kB
Page Count 9
Starting Page 307
Ending Page 315


Source: IEEE Xplore Digital Library