Access Restriction

Author Schaefer, D.H. ♦ Portee, R.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1992
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Concurrent computing ♦ Registers ♦ Petri nets ♦ Hardware ♦ Parallel processing ♦ Software packages ♦ Animation ♦ Nearest neighbor searches ♦ Displays ♦ Flip-flops
Abstract A methodology for the description and analysis of massively parallel computers is presented. Massively parallel structures are modeled with a data path graph, a precedence graph, and a control structure. The control structure, specified with colored Petri nets, employs nomenclature that provides the concise representation of thousands of Petri places and transitions.<<ETX>>
Description Author affiliation: Dept. of Electr. & Comput. Eng., George Mason Univ., Fairfax, VA, USA (Schaefer, D.H.; Portee, R.)
ISBN 0818627727
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1992-10-19
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 402.44 kB
Page Count 8
Starting Page 361
Ending Page 368

Source: IEEE Xplore Digital Library