Access Restriction

Author Jingling Xue
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1994
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Software packages ♦ Software algorithms ♦ Systolic arrays ♦ Algorithm design and analysis ♦ Space technology ♦ Packaging ♦ Oils ♦ Rails ♦ Design methodology ♦ Process design
Abstract Systolic array design consists in the distribution of iterations to both space and time in such a way that the distribution specifies a systolic array. Parallelising compilation consists in the identification of loops whose different iterations may run simultaneously on different processors, either independently or in an overlapped fashion. Both use various matrix transformations such as loop interchange and reversal to detect and exploit parallelism in nested loop algorithms. The paper describes a software package called SysPar for systolising and parallelising nested loop algorithms by unifying these various transformations as nonsingular (unimodular or nonunimodular) transformations.
Description Author affiliation: Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ, Singapore (Jingling Xue)
ISBN 0780318625
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1994-08-22
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 472.96 kB
Page Count 5
Starting Page 551
Ending Page 555

Source: IEEE Xplore Digital Library