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Author Xi Chen ♦ Hsieh, H. ♦ Balarin, F. ♦ Watanabe, Y.
Sponsorship EDAA ♦ EDA Consortium ♦ IEEE Comput. Soc. TTTC ♦ IEEE Comput. Soc. DATC ♦ ECSI ♦ ACM/SIGDA ♦ RAS
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2003
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Lab-on-a-chip ♦ Analytical models ♦ Automatic logic units ♦ System-level design ♦ Logic design ♦ Laboratories ♦ Consumer electronics ♦ Product design ♦ Information analysis ♦ Debugging
Abstract System design methodology is poised to become the next big enabler for highly sophisticated electronic products. Design verification continues to be a major challenge and simulation will remain an important tool for making sure that implementations perform as they should. In this paper we present algorithms to automatically generate C++ checkers from any formula written in the formal quantitative constraint language, logic of constraints (LOC). The executable can then be used to analyze the simulation traces for constraint violation and output debugging information. Different checkers can be generated for fast analysis under different memory limitations. LOC is particularly suitable for specification of system level quantitative constraints where relative coordination of instances of events, not lower level interaction, is of paramount concern. We illustrate the usefulness and efficiency of our automatic trace analysis methodology with case studies on large simulation traces from various system level designs.
Description Author affiliation: Univ. of California, Riverside, CA, USA (Xi Chen; Hsieh, H.)
ISBN 0769518702
ISSN 15301591
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2003-03-07
Publisher Place Germany
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 226.50 kB
Page Count 2
Starting Page 1174
Ending Page 1175

Source: IEEE Xplore Digital Library