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Author Abuhamdeh, Z. ♦ Hannagan, R.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2008
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Delay ♦ Rails ♦ Semiconductor device measurement ♦ Automatic test pattern generation ♦ Biomedical monitoring ♦ Production ♦ Monitoring
Abstract Summary form only given. It is a well known problem that power rail integrity can affect the performance of a chip. This degradation of performance can produce failures in extreme chips built closer to worst case (WC) process and operated under slowest environmental conditions. ATPG delay path can be used to measure the performance of the most vulnerable delay paths of the chip in a production environment and operate as an affective screen for such collective defects in performance and power rail integrity.
Description Author affiliation: TranSwitch Corp., Shelton, CT (Abuhamdeh, Z.; Hannagan, R.)
ISBN 9780769533650
ISSN 15505774
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2008-10-01
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 175.89 kB
Page Count 1
Starting Page 381
Ending Page 381


Source: IEEE Xplore Digital Library