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Author Lei He ♦ Weiping Liao ♦ Stan, M.R.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2004
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Temperature ♦ Thermal management ♦ Power system modeling ♦ Microarchitecture ♦ Energy management ♦ Nanoscale devices ♦ System-on-a-chip ♦ Power system management ♦ Dynamic voltage scaling ♦ Integrated circuit packaging
Abstract The high leakage devices in nanometer technologies as well as the low activity rates in system-on-a-chip (SOC) contribute to the growing significance of leakage power at the system level. We first present system-level leakage-power modeling and characteristics and discuss ways to reduce leakage for caches. Considering the interdependence between leakage power and temperature, we then discuss thermal runaway and dynamic power and thermal management (DPTM) to reduce power and prevent thermal violations. We show that a thermal-independent leakage model may hide actual failures of DPTM. Finally, we present voltage scaling considering DPTM for different packaging options. We show that the optimal Vdd for the hest throughput may be smaller than the largest Vdd allowed by the given packaging platform, and that advanced cooling techniques can improve throughput significantly.
Description Author affiliation: University of California, Los Angeles (Lei He)
ISBN 1511838288
ISSN 0738100X
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2004-07-07
Publisher Place USA
Rights Holder Association for Computing Machinery, Inc. (ACM)
Size (in Bytes) 449.84 kB
Page Count 6
Starting Page 12
Ending Page 17


Source: IEEE Xplore Digital Library