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Author Pasricha, S. ♦ Dutt, N. ♦ Ben-Romdhane, M.
Sponsorship Chinese Inst. of Electron
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2005
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Topology ♦ Throughput ♦ Computer architecture ♦ System-on-a-chip ♦ Protocols ♦ Space exploration ♦ Costs ♦ Broadband communication ♦ Out of order ♦ Embedded computing
Abstract As system-on-chip (SoC) designs become more complex, it becomes increasingly harder to design communication architectures which satisfy design constraints. Manually traversing the vast communication design space for constraint-driven synthesis is not feasible any more. In this paper we propose an approach that automates the synthesis of bus-based communication architectures for systems characterized by (possibly several) throughput constraints. Our approach accurately and effectively prunes the large communication design space to synthesize a feasible low-cost bus architecture which satisfies the constraints in a design.
Description Author affiliation: Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA (Pasricha, S.; Dutt, N.)
ISBN 0780387368
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2005-01-21
Publisher Place China
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 853.88 kB
Page Count 4
Starting Page 495
Ending Page 498


Source: IEEE Xplore Digital Library