Access Restriction

Author Deschacht, D. ♦ Dabrin, C.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1995
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Delay effects ♦ Intelligent networks ♦ Integrated circuit interconnections ♦ Capacitance ♦ Logic gates ♦ Wires ♦ Timing ♦ Inverters ♦ Computational modeling ♦ Circuit simulation
Abstract In all recent technologies the delay caused by interconnection wires is essential in the evaluation of the switching speed of integrated structures. Completely wrong results would result if this were neglected. By considering a distributed RC network to model the interconnection lines, we proposed a new analytical delay time expression for a general tree type network, with full incorporation of technology design parameters. A computationally simple technique is presented and comparisons with HSPICE simulation results show the accuracy of the developed model in timing verification.
Description Author affiliation: Lab. d'Inf., de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France (Deschacht, D.; Dabrin, C.)
ISBN 4930813670
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1995-08-29
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 515.33 kB
Page Count 6
Starting Page 359
Ending Page 364

Source: IEEE Xplore Digital Library