Thumbnail
Access Restriction
Subscribed

Author O'Keefe, S.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1989
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Very large scale integration ♦ Testing ♦ Costs ♦ Pins ♦ Production facilities ♦ Hardware ♦ Automation ♦ Instruments ♦ Resource management ♦ Reconfigurable architectures
Abstract A VLSI tester which can be reconfigured from one high pin count test head to multiple independent lower pin count test heads is described. This reconfigurable resource architecture is shown to provide improved tester utilization for the factory. Greater utilization results in reduced capital equipment costs, thus reducing test costs for the test equipment user. A reconfigurable resource architecture also provides greater flexibility for future upgrades as a result of changing pin count combinations or increased pin count.
Description Author affiliation: Texas Instrum., Dallas, TX, USA (O'Keefe, S.)
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1989-08-29
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 582.11 kB
Page Count 8
Starting Page 597
Ending Page 604


Source: IEEE Xplore Digital Library