Access Restriction

Author Ashok, V. ♦ Costello, R. ♦ Sadayappan, P.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1985
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Circuit simulation ♦ Switches ♦ Computational modeling ♦ Switching circuits ♦ Equations ♦ Parallel processing ♦ Flow graphs ♦ Hardware ♦ Computer architecture ♦ Engines ♦ data-driven computation ♦ switch-level simulation ♦ data-flow ♦ distributed processing
Abstract The complexity of simulating large circuits is a bottleneck in the design process. Considerable attention is being focused on using multiprocessing architectures to speed up simulation. In order to utilize these architectures one first needs to capture the parallelism inherent in the simulation process. This paper explores data flow graphs as a means of expressing the parallelism in switch-level simulation. These data flow graphs, when executed on general purpose or special purpose data flow machines should result in considerable speed up.
Description Author affiliation: Department of Computer and Information Science, The Ohio State University, Columbus, OH (Ashok, V.)
ISBN 0818606355
ISSN 0738100X
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1985-06-23
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 658.18 kB
Page Count 8
Starting Page 637
Ending Page 644

Source: IEEE Xplore Digital Library