Thumbnail
Access Restriction
Subscribed

Author De Luna, L. ♦ Zalewski, Z.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2011
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Other branches of engineering
Subject Keyword Field programmable gate arrays ♦ Vectors ♦ Hardware ♦ Testing ♦ Clocks ♦ Simulation ♦ Analytical models
Abstract RTCA/DO-254, “Design Assurance Guidance for Airborne Electronic Hardware” [1] is currently enforced by the FAA via the Advisory Circular (AC) 20–152 [2] as a means of compliance and guidance for the design assurance of complex electronic hardware such as FPGAs, PLDs and ASICs in airborne systems. RTCA/DO-254 Section 6 (Verification Process) defines a set of verification objectives and methods that present several new challenges to design and verification engineers of airborne electronic hardware. This paper points out the most significant challenges that can be encountered during the hardware verification process of FPGA designs under DO-254 guidelines. More importantly, this paper proposes a verification methodology that replays RTL simulation during hardware testing at full speed utilizing the same simulation testbench as test vectors.
Description Author affiliation: Aldec Hardware Division General Manager, Henderson, NV (Zalewski, Z.) || Aldec DO-254 Program Manager, Henderson, NV (De Luna, L.)
ISBN 9781612847979
ISSN 21557209
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2011-10-16
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
e-ISBN 9781612847986
Size (in Bytes) 157.27 kB


Source: IEEE Xplore Digital Library