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Author Bhattacharya, S. ♦ Dey, S. ♦ Sengupta, B.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1997
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Circuit testing ♦ Sequential analysis ♦ Circuit synthesis ♦ Sequential circuits ♦ Automatic test pattern generation ♦ Registers ♦ Logic design ♦ Reconfigurable logic ♦ Logic circuits ♦ Logic testing
Abstract This paper introduces a low overhead test methodology, RT-SCAN, applicable to RT Level designs. The methodology enables using combinational test patterns for testing the circuit, as done by traditional full-scan or parallel-scan schemes. However, by exploiting existing connectivity of registers through multiplexors and functional units, RT-SCAN reduces area overhead and test application times significantly compared to full-scan and parallel-scan schemes. Unlike most of the existing high-level test synthesis and test generation schemes which can be most effectively applied to data-flow/arithmetic intensive designs like DSPs and processor designs, the RT-SCAN test scheme can be applied to designs from any application domain, including control-flow intensive designs.
Description Author affiliation: C&C Res. Labs., NEC USA, Princeton, NJ, USA (Bhattacharya, S.)
ISBN 0818677864
ISSN 10661409
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1997-03-17
Publisher Place France
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 761.38 kB
Page Count 7
Starting Page 146
Ending Page 152

Source: IEEE Xplore Digital Library