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Author Rincon, A.M. ♦ Trick, M. ♦ Guzowski, T.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1996
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Design methodology ♦ Clocks ♦ Application specific integrated circuits ♦ Design for testability ♦ Wire ♦ Timing ♦ Delay ♦ Process design ♦ Automatic testing ♦ Automatic test pattern generation
Abstract This paper describes the methodology used to design a family of ASIC chips in the 400 K to one-million-gate range in a 0.5 micron technology. Working first-pass hardware was produced at an average clock speed of 100 MHz with over 99% testability. The methodology utilized a variety of third-party CAD tools from Synopsys and Cadence in combination with proprietary IBM tools.
Description Author affiliation: IBM Microelectron., Essex Junction, VT, USA (Rincon, A.M.; Trick, M.; Guzowski, T.)
ISBN 0780331176
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1996-05-05
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 835.74 kB
Page Count 8
Starting Page 45
Ending Page 52

Source: IEEE Xplore Digital Library