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Author Chakraborty, A. ♦ Sithambaram, P. ♦ Duraisami, K. ♦ Macii, A. ♦ Macii, E. ♦ Poncino, M.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2006
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Clocks ♦ Optimization methods ♦ Temperature ♦ Timing ♦ Topology ♦ Thermal resistance ♦ Power system interconnection ♦ Energy management ♦ Power system management ♦ Frequency
Abstract The existence of non-uniform thermal gradients on the substrate in high performance IC's can significantly impact the performance of global on-chip interconnects. This issue is further exacerbated by the aggressive scaling and other factors such as dynamic power management schemes and non-uniform gate level switching activity. In high-performance systems, one of the most important problems is clock skew minimization since it has a direct impact on the maximum operating frequency of the system. Since clocks are routed across the entire chip, the presence of thermal gradients can significantly alter their characteristics because wire resistance increases linearly as the temperature increases. This often results in failure to meet original timing constraints thereby rendering the original topology unusable. Therefore it is necessary to perform a temperature aware re-embedding of the original topology to meet timing under these temperature effects. This work primarily explores these issues by proposing two algorithms that re-structure an existing clock tree topology to compensate for such temperature effects and as a result also meet timing constraints
Description Author affiliation: DAUIN, Politecnico di Torino (Chakraborty, A.; Sithambaram, P.; Duraisami, K.; Macii, A.; Macii, E.; Poncino, M.)
ISBN 3981080114
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2006-03-06
Publisher Place Germany
Rights Holder European Design Automation Association (EDAA)
Size (in Bytes) 304.15 kB


Source: IEEE Xplore Digital Library