Thumbnail
Access Restriction
Subscribed

Author Gschwind, G. ♦ Maurer, D.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1996
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Kernel ♦ Hardware ♦ Communication system control ♦ Pipelines ♦ Software performance ♦ Instruction sets ♦ Computer architecture ♦ Asynchronous communication ♦ Proposals ♦ Economic forecasting
Abstract This paper discusses the design of a MIPS-I processor kernel using VHDL. The control structure of this processor is distributed with a small controller in each pipeline stage controlling sequencing of operations and communication with adjacent pipeline stages. Instruction flow management is performed using asynchronous communication signals. Due to its high-level description and distributed control structure, the kernel can easily be extended. Thus, instruction set extension hardware/software co-evaluation can be performed efficiently using rapid prototyping.
Description Author affiliation: Tech. Univ. Wien, Austria (Gschwind, G.)
ISBN 081867573X
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1996-09-16
Publisher Place Switzerland
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 704.00 kB
Page Count 6
Starting Page 548
Ending Page 553


Source: IEEE Xplore Digital Library