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Author Henderson, C.L. ♦ Soden, J.M.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1997
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Failure analysis ♦ Laboratories ♦ CMOS technology ♦ Integrated circuit modeling ♦ CMOS integrated circuits ♦ Bayesian methods ♦ Statistics ♦ Integrated circuit testing ♦ Mathematical model ♦ Semiconductor device modeling
Abstract A method of signature analysis is presented that is based on ATE data, experiential knowledge of failure modes and mechanisms, or a combination of both. This method can be used on low numbers of failures or even single failures. It uses the Dempster-Shafer theory to calculate failure mechanism confidence. This method can be used for rapid diagnosis of complex IC failures. The model is developed and an example is given based on Sandia's 0.5 /spl mu/m CMOS IC technology.
Description Author affiliation: Electron. Quality Reliability Center, Sandia Nat. Labs., Albuquerque, NM, USA (Henderson, C.L.)
ISBN 0780342097
ISSN 10893539
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1997-11-06
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 1.60 MB
Page Count 9
Starting Page 310
Ending Page 318


Source: IEEE Xplore Digital Library