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Author Furtek, F. ♦ Stone, G. ♦ Jones, I.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1990
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Registers ♦ Computer architecture ♦ Circuit testing ♦ Reconfigurable logic ♦ Logic arrays ♦ Software performance ♦ Flexible printed circuits ♦ Adders ♦ Parallel algorithms ♦ Fabrication
Abstract As a RAM-based reconfigurable logic array, Labyrinth provides the flexibility and malleability of software with the performance of a dedicated circuit. With a single bit register and a half adder per cell, the architecture is optimized for register intensive, massively parallel algorithms. The fine-grained, highly-symmetric architecture scales very naturally and facilitates compact circuit layouts. A 64-cell test chip has been successfully built and tested, and a 4096-cell chip is in the final stages of preparation for fabrication.<<ETX>>
Description Author affiliation: Concurrent Logic Inc., Arlington, MA, USA (Furtek, F.)
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1990-05-13
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 229.33 kB

Source: IEEE Xplore Digital Library