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Author Schulz, M.H. ♦ Fink, F. ♦ Fuchs, K.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1989
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Delay ♦ Circuit faults ♦ Circuit testing ♦ Fault detection ♦ Timing ♦ Computational modeling ♦ Circuit simulation ♦ Permission ♦ Logic testing ♦ Parallel processing
Abstract This paper presents an accelerated fault simulation approach for path delay faults. The distinct features of the proposed fault simulation method consist in the application of parallel processing of patterns at all stages of the calculation procedure, its versatility to account for both robust and non-robust detection of path delay faults, and its capability of efficiently maintaining large numbers of path faults to be simulated.
Description Author affiliation: Institute of Computer Aided Design, Department of Electrical Engineering, Technical University of Munich, Munich, West Germany (Schulz, M.H.)
ISBN 0897913108
ISSN 0738100X
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1989-06-25
Publisher Place USA
Rights Holder Association for Computing Machinery, Inc. (ACM)
Size (in Bytes) 840.25 kB
Page Count 7
Starting Page 357
Ending Page 363


Source: IEEE Xplore Digital Library